Pulse evaluate logic-latch
View Patent ↗A pulse clock is generated by a pulse generator from a system clock. This pulse determines when the output of a high fan-in gate is to be latched. The pulse clock also feeds a latch with no pass gate and sets the timing of the high fan-in dynamic gate. Because of the length of the active time of the pulse clock, the high fan-in dynamic gate does not have a holder.
1. A dynamic logic gate, comprising:
pulse generator generating a pulse clock from a system clock;
high fan-in dynamic gate receiving said pulse clock wherein said pulse clock sets the timing of said dynamic gate and wherein said high fan-in dynamic gate is without a holder on an output node; and,
latch receiving said pulse clock and also receiving a dynamic signal on said output node of said high fan-in dynamic gate, wherein said latch is without a pass gate connected to said dynamic output node.
2. The dynamic logic gate of claim 1 wherein said high fan-in dynamic gate is a high fan-in OR gate.
3. The dynamic logic gate of claim 1 wherein said high fan-in dynamic gate is a high fan-in MUX.
4. The dynamic gate of claim 1 wherein said high fan-in dynamic gate has only one output node.
5. A pulse evaluate logic-latch, comprising:
pulse generator for generating a pulse of short duration from a system clock; and,
dynamic logic gate and a dynamic latch controlled by said pulse to latch an output of said dynamic logic gate, wherein said dynamic logic gate and said dynamic latch are integrated so that they share a common node and said dynamic logic gate does not have a holder on said common node and said dynamic latch and wherein said dynamic logic latch does not have a pass gate through which a signal output on said node common must pass before being latched.
6. The dynamic logic gate of claim 5 wherein said dynamic gate is a high fan-in OR gate.
7. The dynamic logic gate of claim 1 wherein said dynamic gate is a high fan-in MUX.
8. A pulse evaluate logic-latch, comprising: pulse generating means that generate a pulse of short duration from a clock means;
logic means that perform a high fan-in logic function in response to said pulse of short duration to produce an output on an output node, wherein said output node does not have a holder circuit for holding said output during said pulse of short duration; and,
latching means that latch said output, wherein said output is not passed through a pass gate before being latched by a feedback circuit.
9. The dynamic logic gate of claim 5 wherein said dynamic gate is a high fan-in OR gate.
10. The dynamic logic gate of claim 1 wherein said dynamic gate is a high fan-in MUX.