IP Library Granted Patent US 7,230,314
Granted Patent B2
US 7,230,314 · App. 10/400,541 · Granted Jun 12, 2007

Semiconductor device and method of forming a semiconductor device

Assignee: Cambridge Semiconductor Limited
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,230,314
App. No.
10/400,541
Granted
Jun 12, 2007
Kind
B2
Abstract

A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Claims (15)

1. A semiconductor device having an active region that generates heat during normal operation of the device, at least a portion of the active region being provided in a membrane having opposed top and bottom surfaces, one or more support legs being provided adjacent the membrane, the top surface of the membrane having electrical connections made thereto, the bottom surface of the membrane having a heat conducting and electrically insulating layer positioned adjacent thereto, the heat conducting and electrically insulating layer having a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

2. A device according to claim 1 , comprising at least two semiconductor substrate legs between which the membrane is provided.

3. A device according to claim 1 , wherein the whole of the active region is provided in the membrane.

4. A device according to claim 1 , wherein the membrane comprises a semiconductor layer provided on an electrically insulating layer.

5. A device according to claim 1 , wherein the heat conducting and electrically insulating layer comprises at least one of diamond, boron nitride, aluminum oxide and aluminum nitride.

6. A device according to claim 1 , wherein the heat conducting and electrically insulating layer is deposited at lower temperatures compared to the temperatures used in processing the active structure of the device.

7. A device according to claim 1 , wherein the membrane includes a mechanically strong and electrically insulating layer between said at least a portion of the active region and the heat conducting and electrically insulating layer.

8. A semiconductor device according to claim 1 , wherein the active region is provided in a layer, the layer being provided on a semiconductor substrate, at least a portion of the semiconductor substrate below at least a portion of the active region being removed such that said at least a portion of the active region is provided in the membrane defined by that portion of the layer below which the semiconductor substrate has been removed.

9. A device according to claim 8 , comprising at least two semiconductor substrate legs between which the membrane is provided.

10. A device according to claim 8 , wherein the whole of the active region is provided in the membrane.

11. A device according to claim 8 , wherein the membrane comprises a semiconductor layer provided on an electrically insulating layer.

12. A device according to claim 8 , wherein the heat conducting and electrically insulating layer comprises at least one of diamond, boron nitride, aluminum oxide and aluminum nitride.

13. A device according to claim 8 , wherein the heat conducting and electrically insulating layer is deposited at lower temperatures compared to the temperatures used in processing the active structure of the device.

14. A device according to claim 8 , wherein the membrane includes a mechanically strong and electrically insulating layer between said at least a portion of the active region and the heat conducting and electrically insulating layer.

15. A semiconductor device according to claim 8 , wherein at least a portion of the semiconductor substrate remains to provide one or more support legs to the membrane.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2015
From: CAMBRIDGE SEMICONDUCTOR LIMITED
To: CAMBRIDGE MICROELECTRONICS LTD.
Reel/Frame 035562/0533 →
DEBENTURE Recorded Aug 20, 2007
From: ETV CAPITAL S.A.
To: CAMBRIDGE SEMICONDUCTOR LIMITED
Reel/Frame 019714/0643 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2003
From: UDREA, FLORIN; AMARATUNGA, GEHAN A.J.
To: CAMBRIDGE SEMICONDUCTOR LIMITED
Reel/Frame 013925/0214 →
Continuity (3)
Division 0995760900 · Sep 21, 2001
Provisional Application 6023429200 · Sep 21, 2000
Related Publication 20030183923A1 · Oct 2, 2003