Method of setting back bias of MOS circuit, and MOS integrated circuit
View Patent ↗In a MOS circuit comprising a plurality of MOSFETs constituting a digital circuit, an input signal is supplied to the digital circuit, and a first back bias voltage is supplied to a semiconductor substrate or a semiconductor well region in which the MOSFETs are formed, so that a pn junction between the semiconductor substrate or the semiconductor well region and a source region is brought to a forward voltage. In a non-operating state in which a circuit operation is suspended by the input signal supplied to the digital circuit as a fixed level, a second back bias voltage is applied to the semiconductor substrate or the semiconductor well region so that the pn junction between the semiconductor substrate or the semiconductor well region and the source region is brought to a reverse voltage.
1. A semiconductor integrated circuit including a plurality of operation modes, comprising:
a plurality of circuit blocks, each comprising a plurality of P channel MOS transistors, and a plurality of N channel MOS transistors,
wherein said plurality of circuit blocks include a first circuit block and a second circuit block,
wherein said operation modes include a first mode and a second mode,
wherein said N channel MOS transistors included in said first circuit block are provided a bias voltage higher than a ground voltage in said first mode, and are provided a bias voltage lower than said ground voltage in said second mode,
wherein said P channel MOS transistors included in said first circuit block are provided a bias voltage lower than a power supply voltage in said first mode, and are provided a bias voltage higher than said power supply voltage in said second mode,
wherein said N channel MOS transistors included in said second circuit block are provided a bias voltage lower than said ground voltage in said second mode,
wherein said P channel MOS transistors included in said second circuit block are provided a bias voltage higher than said power supply voltage in said second mode,
wherein said N channel MOS transistors included in said second circuit block are provided a bias voltage equal to said ground voltage in said first mode, and
wherein said P channel MOS transistors included in said second circuit block are provided a bias voltage equal to said power supply voltage in said first mode.
2. A semiconductor integrated circuit according to claim 1 , further comprising a bias voltage control circuit which controls bias voltages of said plurality of circuit blocks.
3. A semiconductor integrated circuit according to claim 1 , further comprising a bias voltage providing circuit which generates a plurality of bias voltages corresponding to said plurality of operation modes.