IP Library Granted Patent US 6,996,163
Granted Patent B2
US 6,996,163 · App. 10/402,039 · Granted Feb 7, 2006

Walsh-Hadamard decoder

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Quick Facts
Patent No.
US 6,996,163
App. No.
10/402,039
Granted
Feb 7, 2006
Kind
B2
Abstract

In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.

Claims (9)

1. A Fast Hadamard Transform (“FHT”) engine comprising:

a controller to generate a phase-select signal, the phase select signal indicating whether the FHT engine is in a partitioning phase or a processing phase;

a first memory;

a second memory;

a first add/subtract module configured to receive an input sequence representing a signal, and to output intermediate values to the first memory and the second memory in response to the phase-select signal indicating the partitioning phase;

wherein the first add/subtract module is configured receive intermediate values stored in the first memory, and to replace the received intermediate values in the first memory with the output of the first add/subtract module in response to the phase-select signal indicating the processing phase.

2. The FHT engine of claim 1 , further comprising a second add/subtract module configured to receive intermediate values stored in the second memory, and to replace the received intermediate values in the second memory with the output of the second add/subtract module in response to the phase-select signal indicating the processing phase.

3. The FHT engine of claim 2 , wherein the controller further generates a first and second memory address signal,.the first and second memory address identifying the two intermediate values in both the first and second memories that are to be replaced using the first and second add/subtract modules respectively.

4. The FHT engine of claim 1 , wherein the first memory and the second memory each comprise a dual-port random access memory (RAM).

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED ON REEL 020741 FRAME 0580. ASSIGNOR(S) HEREBY CONFIRMS THE NATURE OF CONVEYANCE IS AN ASSIGNMENT AND NOT A CHANGE OF NAME. Recorded Nov 12, 2008
From: ARRAYCOMM, INC.
To: ARRAYCOMM LLC.
Reel/Frame 021817/0854 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2008
From: ARRAYCOMM LLC
To: INTEL CORPORATION
Reel/Frame 021794/0107 →
CHANGE OF NAME Recorded Apr 2, 2008
From: ARRAYCOMM, INC.
To: ARRAYCOMM LLC
Reel/Frame 020741/0580 →