Optimization of decoder instance memory consumed by the jitter control module
View Patent ↗A decoder for decompressing real-time media data streams and a method for operating such a decoder is disclosed. The decoder may comprise a relatively larger first memory for storing compressed data and parameters, and a processor for executing a decompression algorithm, the processor having a relatively smaller second memory. The decompression algorithm may be executed on a periodic basis, and the parameters used to select the data to be decompressed may be moved from the second memory to the first memory each time the decompression algorithm executes. An embodiment of the present invention may use slower, less expensive memory to enable it to support a greater number of real-time media streams than prior art solutions. Another embodiment of the present invention may include machine-readable storage having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the foregoing.
1. A method of operating a decoder for decoding a real-time media stream, the method comprising:
receiving a plurality of data packets, each of the plurality of data packets comprising header data and payload data;
parsing each of the plurality of data packets into a header data portion and a payload data portion;
storing the header data portions in a first memory, thereby forming a block of header data;
storing the payload data portions in the first memory, thereby forming a block of payload data;
copying the block of header data to a second memory;
decoding at least a portion of the block of payload data using the block of header data in the second memory; and
moving at least a modified portion of the block of header data in the second memory to the first memory.
2. The method of claim 1 wherein the payload data comprises compressed speech data.
3. The method of claim 1 wherein the header data comprises at least one of a time stamp, a sequence number, a jitter estimate, and a reference to a location within the first memory.
4. The method of claim 1 wherein the second memory and a digital signal processor are contained within a single integrated circuit device.
5. The method of claim 1 wherein the size of the second memory is a fraction of the size of the first memory.
6. The method of claim 1 wherein the copying, decoding, and moving occur on a periodic basis.
7. The method of claim 6 wherein copying, decoding, and moving occurs at regular time intervals.
8. The method of claim 1 wherein the first memory has a first speed of access and the second memory has a second speed of access faster than the first speed of access.
9. The method of claim 1 wherein the first memory and a digital signal processor are contained within separate integrated circuit devices.
10. The method of claim 1 wherein the plurality of data packets is received over a wireless network.
11. A machine-readable storage, having stored thereon a computer program having a plurality of code sections for implementing a decoder for decoding a real-time media stream ,the code sections executable by a machine for causing the machine to perform the operations comprising:
receiving a plurality of data packets, each of the plurality of data packets comprising header data and payload data;
parsing each of the plurality of data packets into a header data portion and a payload data portion;
storing the header data portions in a first memory, thereby forming a block of header data;
storing the payload data portions in the first memory, thereby forming a block of payload data;
copying the block of header data to a second memory;
decoding at least a portion of the block of payload data using the block of header data in the second memory; and
moving at least a modified portion of the block of header data in the second memory to the first memory.
12. The machine-readable storage of claim 11 wherein the payload data comprises compressed speech data.
13. The machine-readable storage of claim 11 wherein the header data comprises at least one of a time stamp, a sequence number, a jitter estimate, and a reference to a location within the first memory.
14. The machine-readable storage of claim 11 wherein the second memory and a digital signal processor are contained within a single integrated circuit device.
15. The machine-readable storage of claim 11 wherein the size of the second memory is at least an order of magnitude smaller than the size of the first memory.
16. The machine-readable storage of claim 11 wherein the copying, decoding and moving occur on a periodic basis.
17. The machine-readable storage of claim 16 wherein copying, decoding, and moving occurs at regular time intervals.
18. The machine-readable storage of claim 11 wherein the first memory has a first speed of access and the second memory has a second speed of access faster than the first speed of access.
19. The machine-readable storage of claim 11 wherein the first memory and a digital signal processor are contained within separate integrated circuit devices.
20. The machine-readable storage of claim 11 wherein the plurality of data packets is received over a wireless network.
21. One or more circuits for decoding a real-time media stream, the one or more circuits comprising:
at least one processor enabled to receive a plurality of data packets, each of the plurality of data packets comprising header data and payload data, the at least one processor operable to, at least:
parse each of the plurality of data packets into a header data portion and a payload data portion;
store the header data portions in a first memory, thereby forming a block of header data;
store the payload data portions in the first memory, thereby forming a block of payload data;
copy the block of header data to a second memory;
decode at least a portion of the block of payload data using the block of header data in the second memory; and
move at least a modified portion of the block of header data in the second memory to the first memory.
22. The one or more circuits of claim 21 wherein the payload data comprises compressed speech data.
23. The one or more circuits of claim 21 wherein the header data comprises at least one of a time stamp, a sequence number, a jitter estimate, and a reference to a location within the first memory.
24. The one or more circuits of claim 21 wherein the second memory and a digital signal processor are contained within a single integrated circuit device.
25. The one or more circuits of claim 21 wherein the size of the second memory is a fraction of the size of the first memory.
26. The one or more circuits of claim 21 wherein the copying, decoding, and moving occur on a periodic basis.
27. The one or more circuits of claim 21 wherein copying, decoding, and moving occurs at regular time intervals.
28. The one or more circuits of claim 21 wherein the first memory has a first speed of access and the second memory has a second speed of access faster than the first speed of access.
29. The one or more circuits of claim 21 wherein the first memory and a digital signal processor are contained within separate integrated circuit devices.
30. The one or more circuits of claim 21 wherein the plurality of data packets is received over a wireless network.