Error word generation with multiple element input

1. A method comprising:

receiving a plurality of data elements of a data stream; and

updating an error word for the data stream by processing the plurality of data elements in a single iteration, updating the error word comprising performing a linear operation on the plurality of data elements and a previous value of the error word;

wherein performing the linear operation comprises applying a first linear operator to the previous value of the error word and applying a second linear operator to the plurality of data elements, and wherein applying the first linear operator comprises multiplying the previous value of the error word by a first matrix constant R 1 equal to A k , where A is a state transition matrix for a linear feedback shift register and k is the number of data elements received.

2. The method of claim 1 , wherein k is equal to any number of data elements greater than one.

3. The method of claim 1 , further comprising combining the result of the first linear operator with the result of the second linear operator to produce the updated error word.

4. The method of claim 1 , wherein the plurality of data elements are received in parallel.

5. The method of claim 4 , wherein the data elements are processed without conversion of the data elements from parallel to serial.

6. The method of claim 1 , wherein the error word is a cyclic redundancy check (CRC) word.

7. A method comprising:

receiving a plurality of data elements of a data stream; and

updating an error word for the data stream by processing the plurality of data elements in a single iteration, updating the error word comprising performing a linear operation on the plurality of data elements and a previous value of the error word;

wherein performing the linear operation comprises applying a first linear operator to the previous value of the error word and applying a second linear operator to the plurality of data elements, wherein applying the second linear operator comprises multiplying the plurality of data elements by a second matrix constant R 2 equal to:

R 2 =[A k−1 b A k−2 b . . . Ab b]

where b is an input matrix for the linear feedback shift register.

8. The method of claim 7 , further comprising combining the result of the first linear operator with the result of the second linear operator to produce the updated error word.

9. The method of claim 7 , wherein the plurality of data elements are received in parallel.

10. The method of claim 9 , wherein the data elements are processed without conversion of the data elements from parallel to serial.

11. The method of claim 7 , wherein the error word is a cyclic redundancy check (CRC) word.

12. A method comprising:

receiving a data stream;

processing a plurality of elements of the data stream in each of a plurality of iterations, processing the plurality of data elements comprising performing a linear operation on the plurality of data elements and a previous value of the error word, wherein performing the linear operation comprises applying a first linear operator to the previous value of the error word and applying a second linear operator to the plurality of data elements; and

producing an error word for the data stream based on the processing of the elements of the data stream; wherein applying the first linear operator comprises multiplying the previous interim result by a first matrix constant R 1 equal to A k , where A is a state transition matrix for a linear feedback shift register and k is the number of data elements received.

13. The method of claim 12 , wherein k is an arbitrary number of data elements.

14. The method of claim 12 , further comprising combining the result of the first linear operator with the result of the second linear operator to produce an interim result.

15. The method of claim 12 , wherein the plurality of data elements are received in parallel.

16. The method of claim 15 , wherein the data elements are processed without conversion of the data elements from parallel to serial.

17. The method of claim 12 , wherein the error word is a cyclic redundancy check (CRC) word.

18. A method comprising:

receiving a data stream;

processing a plurality of elements of the data stream in each of a plurality of iterations, processing the plurality of data elements comprising performing a linear operation on the plurality of data elements and a previous value of the error word, wherein performing the linear operation comprises applying a first linear operator to the previous value of the error word and applying a second linear operator to the plurality of data elements; and

producing an error word for the data stream based on the processing of the elements of the data stream;

wherein applying the second linear operator comprises multiplying the plurality of data elements by a second matrix constant R 2 equal to:

R 2 =[A k−1 b A k−2 b . . . Ab b]

where b is an input matrix for the linear feedback shift register.

19. The method of claim 18 , further comprising combining the result of the first linear operator with the result of the second linear operator to produce an interim result.

20. The method of claim 18 , wherein the plurality of data elements are received in parallel.

21. The method of claim 20 , wherein the data elements are processed without conversion of the data elements from parallel to serial.

22. The method of claim 18 , wherein the error word is a cyclic redundancy check (CRC) word.

23. An error word generator comprising:

an input to receive a data stream; and

an operator to process a plurality of data elements in a single clock cycle, the operator to perform a first linear operation on the plurality of data elements and a second linear operation on a previous interim result;

wherein the first linear operation comprises multiplying the previous interim result by a first matrix constant R 1 to produce a first result, and wherein the first matrix constant R 1 is equal to A k , where A is a state transition matrix for a linear feedback shift register and k is the number of data elements received.

24. The error word generator of claim 23 , wherein k is equal to any number of data elements greater than one.

25. The error word generator of claim 23 , wherein the operator is to combine the result of the first linear operation with the result of the second linear operation to produce an interim result.

26. The error word generator of claim 23 , wherein the plurality of data elements are received in parallel.

27. The error word generator of claim 26 , wherein the data elements are processed without conversion of the data elements from parallel to serial.

28. The error word generator of claim 23 , wherein the error word is a cyclic redundancy check (CRC) word.

29. An error word generator comprising:

an input to receive a data stream; and

an operator to process a plurality of data elements in a single clock cycle, the operator to perform a first linear operation on the plurality of data elements and a second linear operation on a previous interim result;

wherein the second linear operation comprises multiplying the plurality of data elements by a second matrix constant R 2 to produce a second result, the second matrix constant R 2 being equal to:

R 2 =[A k−1 b A k−2 b . . . Ab b]

where b is an input matrix for the linear feedback shift register.

30. The error word generator of claim 29 , wherein the operator is to combine the result of the first linear operation with the result of the second linear operation to produce an interim result.

31. The error word generator of claim 29 , wherein the plurality of data elements are received in parallel.

32. The error word generator of claim 31 , wherein the data elements are processed without conversion of the data elements from parallel to serial.

33. The error word generator of claim 29 , wherein the error word is a cyclic redundancy check (CRC) word.

34. A method of producing an error word for a data stream comprising:

receiving a data stream, k data elements of the data stream being received for each of a plurality of iterations, k being greater than or equal to two;

producing a new interim result in each of the plurality of iterations, the new interim result being based on the plurality of data elements and a previous interim result, producing the interim result comprising applying a first linear operator to the k data elements and applying a second linear operator to the previous interim result; and

storing the new interim result from each iteration for use in a following iteration;

wherein applying the first linear operator comprises multiplying the previous interim result by a first matrix constant R 1 equal to A k , where A is a state transition matrix for a linear feedback shift register.

35. The method of claim 34 , wherein producing the interim result further comprises combining the result of the first linear operator with the result of the second linear operator to produce the interim result.

36. The method of claim 34 , wherein the k data elements are received in parallel.

37. The method of claim 36 , wherein the k data elements are processed without conversion of the data elements from parallel to serial.

38. The method of claim 34 , wherein the error word is a cyclic redundancy check (CRC) word.

39. A method of producing an error word for a data stream comprising:

receiving a data stream, k data elements of the data stream being received for each of a plurality of iterations, k being greater than or equal to two;

producing a new interim result in each of the plurality of iterations, the new interim result being based on the plurality of data elements and a previous interim result, producing the interim result comprising applying a first linear operator to the k data elements and applying a second linear operator to the previous interim result; and

storing the new interim result from each iteration for use in a following iteration;

wherein applying the second linear operator comprises multiplying the k data elements by a second matrix constant R 2 equal to:

R 2 =[A k−1 b A k−2 b . . . Ab b]

where b is an input matrix for the linear feedback shift register.

40. The method of claim 39 , wherein producing the interim result further comprises combining the result of the first linear operator with the result of the second linear operator to produce the interim result.

41. The method of claim 39 , wherein the k data elements are received in parallel.

42. The method of claim 41 , wherein the k data elements are processed without conversion of the data elements from parallel to serial.

43. The method of claim 39 , wherein the error word is a cyclic redundancy check (CRC) word.

44. An interchangeable computer adapter card comprising:

a master control unit to control operations performed on the card;

a radio section to transmit and receive radio signals to and from the card;

a physical layer processor comprising an error word generator, the error word generator comprising:

an input to receive a data stream, and

an operator to process a plurality of data elements in a single clock cycle, the operator to perform a first linear operation on the plurality of data elements and a second linear operation on a previous interim result;

wherein the first linear operation comprises multiplying the previous interim result by a first matrix constant R 1 to produce a first result, the first matrix constant R 1 being equal to A k , where A is a state transition matrix for a linear feedback shift register and k is the number of data elements received.

45. The adaptor card of claim 44 , wherein k is an arbitrary number of data elements greater than or equal to two.

46. The adapter card of claim 44 , wherein the operator is to combine the result of the first linear operation with the result of the second linear operation to produce an interim result.

47. The adapter card of claim 44 , wherein the plurality of data elements are received in parallel.

48. The adapter card of claim 47 , wherein the data elements are processed without conversion of the data elements from parallel to serial.

49. The adapter card of claim 44 , wherein the error word is a cyclic redundancy check (CRC) word.

50. An interchangeable computer adapter card comprising:

a master control unit to control operations performed on the card;

a radio section to transmit and receive radio signals to and from the card;

a physical layer processor comprising an error word generator, the error word generator comprising:

an input to receive a data stream, and

an operator to process a plurality of data elements in a single clock cycle, the operator to perform a first linear operation on the plurality of data elements and a second linear operation on a previous interim result;

wherein the second linear operation comprises multiplying the plurality of data elements by a second matrix constant R 2 to produce a second result, the second matrix constant R 2 being equal to:

R 2 =[A k−1 b A k−2 b . . . Ab b]

where b is an input matrix for the linear feedback shift register.

51. The adapter card of claim 50 , wherein the operator is to combine the result of the first linear operation with the result of the second linear operation to produce an interim result.

52. The adapter card of claim 50 , wherein the plurality of data elements are received in parallel.

53. The adapter card of claim 52 , wherein the data elements are processed without conversion of the data elements from parallel to serial.

54. The adapter card of claim 50 , wherein the error word is a cyclic redundancy check (CRC) word.