Low-k dielectric layer with overlying adhesion layer
View Patent ↗In one embodiment, a method of fabricating an integrated circuit includes forming a low-k dielectric layer over metal lines, forming an adhesion layer over the low-k dielectric layer, and forming a capping layer over the adhesion layer. The low-k dielectric may comprise SiLK™ dielectric material, while the capping layer may comprise TEOS. The resulting stack of dielectric materials may be employed in a passivation level to protect the metal lines. For example, a topside layer may be formed over the capping layer.
1. A method of fabricating an integrated circuit, the method comprising:
forming a low-k dielectric layer over metal lines, the metal lines being in a metal level just below a passivation level;
forming an adhesion layer on the low-k dielectric layer;
forming a dielectric capping layer on the adhesion layer; and
depositing a topside layer over the dielectric capping layer.
2. The method of claim 1 wherein the low-k dielectric layer comprises a dielectric material having a dielectric constant of about 2.65.
3. The method of claim 1 wherein the adhesion layer comprises an adhesion promoter.
4. The method of claim 1 wherein the adhesion layer is formed to a thickness of about 70 Angstroms.
5. The method of claim 1 wherein the low-k dielectric layer substantially fills spaces between the metal lines.
6. The method of claim 1 wherein the topside layer comprises silicon nitride.
7. A structure in an integrated circuit, the structure comprising:
a low-k dielectric layer over metal lines, wherein the low-k dielectric layer substantially fills spaces between the metal lines;
an adhesion layer on the low-k dielectric layer;
a dielectric capping layer on the adhesion layer; and
a topside layer on the dielectric capping layer.
8. The structure of claim 7 wherein the low-k dielectric layer has a dielectric constant of about 2.65.
9. The structure of claim 7 wherein the adhesion layer comprises an adhesion promoter.
10. The structure of claim 7 wherein the adhesion layer is about 70 Angstroms thick.
11. A method of forming a passivation level in an integrated circuit, the method comprising:
forming a low-k dielectric layer over metal lines in a last metal level;
forming an adhesion layer over the low-k dielectric layer;
forming a capping layer over the adhesion layer; and
forming a topside layer over the capping layer.
12. The method of claim 11 wherein the adhesion layer comprises an adhesion promoter.
13. The method of claim 11 wherein the capping layer comprises TEOS (tetraethyl ortho-silicate) and the low-k dielectric layer has a dielectric constant of about 2.65.
14. A method of fabricating an integrated circuit, the method comprising:
forming a low-k dielectric layer over metal lines;
forming an adhesion layer on the low-k dielectric layer;
forming a dielectric capping layer on the adhesion layer;
depositing a topside layer over the dielectric capping layer;
wherein the low-k dielectric layer and the adhesion layer are portions of a passivation level.
15. The method of claim 14 wherein the dielectric capping layer comprises silicon dioxide deposited using TEOS (tetraethyl ortho-silicate) as a precursor.
16. The method of claim 14 wherein the low-k dielectric layer substantially fills spaces between the metal lines.
17. The method of claim 14 wherein the dielectric capping layer comprises silicon nitride.
18. A method of fabricating an integrated circuit, the method comprising:
forming a low-k dielectric layer over metal lines;
forming an adhesion layer on the low-k dielectric layer;
forming a dielectric capping layer on the adhesion layer;
depositing a topside layer over the dielectric capping layer;
wherein the dielectric capping layer comprises silicon dioxide deposited using TEOS (tetraethyl ortho-silicate) as a precursor.
19. The method of claim 18 wherein the low-k dielectric layer substantially fills spaces between the metal lines.
20. The method of claim 18 wherein the topside layer comprises silicon nitride.