Built-in self test circuit

1. A built-in self test (BIST) circuit for testing memory block of an LSI, comprising a verification test pattern generator for generating a verification test pattern, wherein said verification test pattern is dedicated to verification of electric connections in the LSI and includes an address pattern that selects only addresses equal to 2 n in said memory block, where n is a positive integer, and wherein said verification test pattern is used for testing connections in said BIST circuit and the memory block as well as connections between said BIST circuit and the memory block.

2. The BIST circuit according to claim 1 , wherein said BIST circuit further includes a scan test pattern generator for generating a scan test pattern, said scan test pattern being dedicated to testing the memory block in a scan path test.

3. The BIST circuit according to claim 1 , wherein said verification test pattern generator includes a shift register.

4. The BIST circuit according to claim 1 , wherein said verification test pattern includes a data pattern which specifies data “1” or “0” as write data, and a command pattern which specifies write or read operation.

5. The BIST circuit according to claim 1 , further comprising another test pattern generator for generating another test pattern which specifies all the addresses in said memory block.

6. The BIST circuit according to claim 1 , wherein said verification test pattern is described in a behavior level language.

7. A method for testing the LSI in a design stage of the LSI by using the BIST circuit according to claim 6 .

8. A method for testing the LSI in a design stage of the LSI by using the BIST circuit according to claim 1 .