Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same

1. A computer implemented method for designing an integrated circuit (IC) floorplan silhouette-like power supply net for an IC having a transistor embedded silicon based substrate and an interconnect structure including at least three metal layers for power routing purposes and transistor interconnection purposes, the IC floorplan silhouette-like power supply net including at least one of a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net, the method comprising the steps of:

(a) receiving (i) an IC floorplan including at least one power consuming entity for electrical connection to the IC floorplan silhouette-like power supply net, a power consuming entity constituting an exempt area, (ii) the designation of one or two metal layers of the interconnect structure assigned to be the supply layers exclusively reserved for the IC floorplan silhouette-like power supply net, and (iii) a SoS net boundary;

(b) for each metal layer, determining a SoS net within the SoS net boundary, each SoS net being the logical complement of all the exempt areas of the IC floorplan within the SoS net boundary; and

(c) outputting information with respect to the IC floorplan silhouette-like power supply net.

2. The method according to claim 1 wherein the SoS net boundary is substantially congruent with the boundary of the IC floorplan.

3. The method according to claim 1 wherein the interconnect structure's two lowermost metal layers are assigned to be the supply layers of the IC floorplan silhouette-like power supply net.

4. The method according to claim 1 and further comprising the step of provisioning a save ring around a power consuming entity, the save ring including non-slotted save ring vertices at the junctures of horizontal save ring regions and vertical save ring regions respectively adjacent the power consuming entity's horizontal edges and vertical edges.

5. The method according to claim 1 and further comprising the step of dividing a SoS net into non-slotted regions, horizontal slot regions intended for provisioning with horizontal slots, vertical slot regions intended for provisioning with vertical slots, and blanks regions intended for provisioning with either horizontal slots or vertical slots.

6. The method according to claim 1 and further comprising the step of applying a minus union algorithm to a SoS net to minimize the number of SoS rectangles uniquely describing its shape.

7. An article of manufacture comprising a recordable medium having recorded thereon a plurality of programming instructions suitable for use to program an apparatus to enable the programmed apparatus to design an integrated circuit (IC) floorplan silhouette-like power supply net for an IC having a transistor embedded silicon based substrate and an interconnect structure including at least three metal layers for power routing purposes and transistor interconnection purposes, the IC floorplan silhouette-like power supply net including at least one of a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net, the programmed apparatus being able to:

(a) receive (i) an IC floorplan including at least one power consuming entity for electrical connection to the IC floorplan silhouette-like power supply net, a power consuming entity constituting an exempt area, (ii) the designation of one or two metal layers of the interconnect structure assigned to be the supply layers exclusively reserved for the IC floorplan silhouette-like power supply net, and (iii) a SoS net boundary;

(b) for each metal layer, determine a SoS net within the SoS net boundary, each SoS net being the logical complement of all the exempt areas of the IC floorplan within the SoS net boundary; and

(c) output information with respect to the IC floorplan silhouette-like power supply net.

8. The article of manufacture according to claim 7 wherein the SoS net boundary is substantially congruent with the boundary of the IC floorplan.

9. The article of manufacture according to claim 7 wherein the interconnect structure's two lowermost metal layers are assigned to be the supply layers of the IC floorplan silhouette-like power supply net.

10. The article of manufacture according to claim 7 wherein the programming instructions enable the programmed apparatus to provision a save ring around a power consuming entity, the save ring including non-slotted save ring vertices at the junctures of horizontal save ring regions and vertical save ring regions respectively adjacent the power consuming entity's horizontal edges and vertical edges.

11. The article of manufacture according to claim 7 wherein the programming instructions enable the programmed apparatus to divide a SoS net into non-slotted regions, horizontal slot regions intended for provisioning with horizontal slots, vertical slot regions intended for provisioning with vertical slots, and blanks regions intended for provisioning with either horizontal slots or vertical slots.

12. The article of manufacture according to claim 7 wherein the programming instructions enable the programmed apparatus to apply a minus union algorithm to a SoS net to minimize the number of SoS rectangles uniquely describing its shape.

13. A computer system for designing an integrated circuit (IC) floorplan silhouette-like power supply net for an IC having a transistor embedded silicon based substrate and an interconnect structure including at least three metal layers for power routing purposes and transistor interconnection purposes, the IC floorplan silhouette-like power supply net including at least one of a V DD Sea-of-Supply (SoS) net and a GND Sea-of-Supply (SoS) net, the system comprising:

(a) one or more storage devices having stored therein a plurality of programming instructions; and

(b) one or processors coupled to the one or more storage devices to execute the programming instructions to receive (i) an IC floorplan including at least one power consuming entity for electrical connection to the IC floorplan silhouette-like power supply net, the power consuming entity constituting an exempt area, (ii) the designation of one or two metal layers of the interconnect structure assigned to be the supply layers exclusively reserved for the IC floorplan silhouette-like power supply net, and (iii) a SoS net boundary; for each metal layer, determining a SoS net within the SoS net boundary, each SoS net being the logical complement of all the exempt areas of the IC floorplan within the SoS net boundary; and output information with respect to the IC floorplan silhouette-like power supply net.

14. The system according to claim 13 wherein the SoS net boundary is substantially congruent with the boundary of the IC floorplan.

15. The system according to claim 13 wherein the interconnect structure's two lowermost metal layers are assigned to be the supply layers of the floorplan silhouette-like power supply net.

16. The system according to claim 13 wherein one of the processors executes the step of provisioning a save ring around a power consuming entity, the save ring including non-slotted save ring vertices at the junctures of horizontal save ring regions and vertical save ring regions respectively adjacent the power consuming entity's horizontal edges and vertical edges.

17. The system according to claim 13 wherein one of the processors executes the step of dividing a SoS net into non-slotted regions, horizontal slot regions intended for provisioning with horizontal slots, vertical slot regions intended for provisioning with vertical slots, and blanks regions intended for provisioning with either horizontal slots or vertical slots.

18. The system according to claim 13 wherein one of the processors execute the step of applying a minus union algorithm to a SoS net to minimize the number of SoS rectangles uniquely describing its shape.