Digital receiver and method
View Patent ↗A receiver and method is provided for sigma-delta converting an RF signal to a digital signal and downconverting to a digital baseband signal. The RF signal is split into N phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (A/D) sigma-delta converter. Polyphase decimation techniques and demodulation are applied to the phased signals to generate a demodulated digital signal. The demodulated digital signal is further downconverted to the appropriate baseband signal.
1. A receiver, comprising:
a sample and hold circuit for receiving and separating a radio frequency (RF) signal into a plurality of parallel sampled analog signals;
an analog-to-digital (A/D) converter for receiving the plurality of parallel sampled analog signals and generating a plurality of parallel digital signals;
a demodulator for receiving and demodulating the parallel digital signals to generate a plurality of demodulated digital signals;
circuitry for receiving the plurality of demodulated digital signals and combining the plurality of demodulated digital signals into a digital signal; and
a digital downconverter for receiving the digital signal having a first rate and downconverting the digital signal to a baseband digital signal having a second rate.
2. The receiver in accordance with claim 1 further comprising:
a low noise amplifier for receiving the RF signal and generating an amplified RF signal; and
an analog bandpass filter for receiving the amplified RF signal and outputting a filtered RF signal for input to the sample and hold circuit.
3. The receiver in accordance with claim 1 further comprising:
a local oscillator for generating a local clocking signal for use by the sample and hold circuit in generating the plurality of parallel sampled analog signals for output.
4. The receiver in accordance with claim 1 wherein the digital signal comprises I and Q signals and the demodulator further functions to demodulate the plurality of modulated digital signals to generate the I and Q signals.
5. The receiver in accordance with claim 1 wherein the sample and hold circuit separates the RF signal into a number N of parallel sampled analog signals, and the circuitry further comprises:
a number N of subfilters for filtering each of the parallel digital signals.
6. The receiver in accordance with claim 1 wherein the sample and hold circuit separates the RF signals into a number a number N of parallel sampled analog signals, and where N is an integer multiple of four, and the circuitry further comprises:
a number N of subfilters for filtering a corresponding number N of parallel sampled digital signals.
7. The receiver in accordance with claim 6 wherein the circuitry comprises a polyphase filter having N subfilters with each subfilter having a set of coefficients, and wherein the coefficients of the subfilters correspond with a set of coefficients of the polyphase filter.
8. The receiver in accordance with claim 7 wherein the polyphase filter comprises a digital finite impulse response filter.
9. The receiver in accordance with claim 7 wherein the digital signal comprises I and Q signals, and wherein the filter coefficients of the subfilters are modified such that subfilter coefficients implement the demodulator for generating the I and Q signals.
10. The receiver in accordance with claim 1 wherein the plurality of parallel digital signals generated by the A/D converter comprise a first sample having one or more binary bits.
11. The receiver in accordance with claim 1 wherein the A/D converter comprises a plurality of A/D sigma-delta converters.
12. A receiver, comprising:
means for receiving and separating a radio frequency (RF) signal into a plurality of parallel sampled analog signals;
means for receiving the plurality of parallel sampled analog signals and generating a plurality of parallel digital signals;
means for receiving and demodulating the parallel digital signals to generate a plurality of demodulated digital signals;
means for receiving the plurality of demodulated digital signals and combining the plurality of demodulated digital signals into a digital signal; and
means for receiving the digital signal having a first rate and downconverting the digital signal to a baseband digital signal having a second rate.
13. The receiver in accordance with claim 12 further comprising:
means for receiving the RF signal and generating an amplified RF signal; and
means for receiving the amplified RF signal and outputting a filtered RF signal for input to the means for receiving and separating the RF signal.
14. A method of downconverting a received analog signal, comprising:
receiving an RF signal;
sampling and separating the RF signal into a plurality of phased analog signals;
analog-to-digital converting the plurality of phased analog signals to generate a plurality of phased digital signals;
combining the plurality of phased digital signals into a digital signal having a first rate; and
downconverting the digital signal to a downconverted digital signal having a second rate.
15. The method in accordance with claim 14 further comprising:
generating a local clocking signal for use in sampling and separating the RF signal into the plurality of phased analog signals.
16. The method in accordance with claim 14 wherein the digital signal comprises I and Q signals and the I and Q signals are generated by demodulating the phased digital signals.
17. The method in accordance with claim 14 wherein a the RF signal is separated into a number N of phased analog signals, and the method further comprises:
filtering each of a number N of phased digital signals with a subfilter.
18. The method in accordance with claim 17 wherein N is an integer multiple of four, and each subfilter comprises a digital finite impulse response function.
19. A wireless communications device, comprising:
a receiver, comprising,
a sample and hold circuit for receiving and separating a radio frequency (RF) signal into a plurality of parallel sampled analog signals,
an analog-to-digital (A/D) converter for receiving the plurality of parallel sampled analog signals and generating a plurality of parallel digital signals,
a demodulator for receiving and demodulating the parallel digital signals to generate a plurality of demodulated digital signals,
circuitry for receiving the plurality of demodulated digital signals and combining the plurality of demodulated digital signals into a digital signal, and
a digital downconverter for receiving the digital signal having a first rate and downconverting the digital signal to a baseband digital signal having a second rate.
20. The wireless communications device in accordance with claim 19 wherein the device is a mobile terminal.
21. The wireless communications device in accordance with claim 19 wherein the device is a base station.