IP Library Granted Patent US 7,920,624
Granted Patent B2
US 7,920,624 · App. 10/404,389 · Granted Apr 5, 2011

Inverse quantizer supporting multiple decoding processes

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Quick Facts
Patent No.
US 7,920,624
App. No.
10/404,389
Granted
Apr 5, 2011
Kind
B2
Abstract

The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device.

Claims (22)

1. An inverse quantizer apparatus for processing macroblocks of data, the apparatus having modular operation elements that can be selectably invoked to accommodate different coding standards, the apparatus comprising:

a memory area having table entries corresponding to the modular operation elements;

a modular operation including a decoder device, whereby the decoder device is selectably invoked via accessing the associated decoder device table entry;

a modular operation including an inverse scan device, whereby the scan device is selectably invoked via accessing the associated scan device table entry;

a modular operation, including a de-quantizer device, wherein the de-quantizer device is selectably invoked via accessing the associated de-quantizer device table entry; and

at least one modular operation, including a processing operation that can be invoked between other modular operations, where the processing operation is selectably invoked via accessing the associated processing operation table entry.

2. The inverse quantizer apparatus of claim 1 , wherein the modular operations are invoked via accessing commands stored in the memory area.

3. The inverse quantizer apparatus of claim 1 , wherein the table entries are pre-loaded into the memory area.

4. The inverse quantizer apparatus of claim 3 , wherein the inverse quantizer apparatus is invoked and the appropriate table will be referenced at the appropriate point in completing the inverse quantizer operation.

5. The inverse quantizer apparatus of claim 1 , wherein the table entries are loaded via a separate command stored in the memory area.

6. The inverse quantizer apparatus of claim 1 , wherein different table entries are loaded depending upon the coding standard being used.

7. The inverse quantizer apparatus of claim 6 , wherein the tables are updated at the macroblock level, whereby the tables can be readily changed according to different coding standards.

8. The inverse quantizer apparatus of claim 1 , wherein the memory storage area includes an SRAM device.

9. The inverse quantizer apparatus of claim 1 , wherein the decoder device is a run level decoder.

10. The inverse quantizer apparatus of claim 1 , wherein certain modular operations can be selectably bypassed.

11. An inverse quantizer apparatus for processing macroblocks of data, the apparatus having modular operation elements that can be selectably invoked to accommodate different coding standards, the apparatus comprising:

a memory area having table entry means corresponding to the modular operation elements;

a first modular operation element including a decoder device;

a second modular operation element including an inverse scan device;

a third modular operation element including a de-quantizer device; and

at least one additional modular operation element including a processing operation that can be invoked between other modular operations,

wherein the modular operations are invoked via a selectable means for accessing the table entry means.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
RE-RECORD TO CORRECT THE NAME OF THE THIRD ASSIGNOR, PREVIOUSLY RECORDED ON REEL 014147 FRAME 0734, ASSIGNOR CONFIRMS THE ASSIGNMENT OF THE ENTIRE INTEREST. Recorded Feb 5, 2004
From: HSIUN, VIVIAN; MACINNIS, ALEXANDER G.; XIE, XIAODONG
To: BROADCOM CORPORATION
Reel/Frame 014309/0949 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2003
From: HSIUN, VIVIAN; MACINNIS, ALEXANDER G.; XIAODONG
To: BROADCOM CORPORATION
Reel/Frame 014147/0734 →