Boundary scan circuit

1. A boundary scan circuit integrated into a Joint Test Action Group (JTAG) device for testing a first circuit in the JTAG device, the first circuit having an input node and an output node, the JTAG device also including a second circuit having an input node coupled to the output node of the first circuit, the boundary scan circuit comprising:

a boundary scan register having a first cell connected to the input node of the first circuit, and a second cell connected between the output node of the first circuit and the input node of the second circuit, the second cell having a latch flip-flop supplying latched data to the second circuit; and

a Test Access Port (TAP) interface controlling the boundary scan register, the TAP interface enabling and disabling a latching operation by the latch flip-flop in the second cell according to an input instruction code.

2. The boundary scan circuit of claim 1 , wherein the input instruction code is a private instruction code.

3. The boundary scan circuit of claim 1 , wherein:

the TAP interface supplies the second cell with a latch clock signal;

the TAP interface also supplies the second cell with a latch enable signal for enabling and disabling the latch clock signal;

the latch flip-flop has a clock input terminal; and

the second cell has a logic circuit for performing a logic operation on the latch clock signal and the latch enable signal and supplying a resulting signal to the clock input terminal of the latch flip-flop.

4. The boundary scan circuit of claim 3 , wherein the logic circuit is an AND gate.

5. The boundary scan circuit of claim 1 , wherein:

the first cell has a shift flip-flop;

the TAP interface supplies the shift flip-flop with a shift clock signal;

the first circuit operates on a system clock signal; and

the system clock signal and the shift clock signal are derived from a single clock tree in the JTAG device.

6. The boundary scan circuit of claim 5 , wherein the shift flip-flop is a negative-edge-triggered flip-flop.

7. The boundary scan circuit of claim 1 , wherein:

the latch flip-flop in the second cell has a set or reset input terminal for setting the latch flip-flop to a predetermined state; and

the TAP interface activates the set or reset input terminal of the latch flip-flop at the beginning of a test of the first circuit.

8. The boundary scan circuit of claim 1 , wherein the first circuit is an intellectual-property core.

9. The boundary scan circuit of claim 1 , wherein the first circuit is a flash controller and the second circuit is a flash memory.

10. A method of testing a first circuit in a JTAG device, the first circuit having an input node and an output node, the JTAG device also including a second circuit and a boundary scan register, the second circuit having an input node coupled to the output node of the first circuit, the boundary scan register having a first cell connected to the input node of the first circuit and a second cell connected between the output node of the first circuit and the input node of the second circuit, the second boundary scan cell having a latch flip-flop supplying latched data to the second circuit, the method comprising;

setting control data in the latch flip-flop for output to the second circuit;

disabling further latching operations by the latch flip-flop;

supplying test input data to the first circuit through the first cell in the boundary scan register;

obtaining test output data from the first input circuit through the second cell in the boundary scan register; and

repeating the steps of supplying test input data and obtaining test output data, the latching operation by the latch flip-flop remaining disabled.

11. The method of claim 10 , wherein the JTAG device also includes a TAP controller, and disabling further latching operation comprises supplying a private instruction code to the TAP controller.

12. The method of claim 10 , wherein the JTAG device also includes a TAP controller, the method further comprising:

supplying an update signal from the TAP controller to the second cell;

supplying an update-enable signal from the TAP controller to the second cell;

performing a logic operation on the update signal and the update-enable signal in the second cell, thereby generating a gated update signal; and

supplying the gated update signal to a clock input terminal of the latch flip-flop.

13. The method of claim 12 , wherein the logic operation is an AND operation.

14. The method of claim 10 , wherein the first cell has a shift flip-flop, the method further comprising:

supplying a system clock signal to the first circuit; and

supplying a shift clock signal from the TAP controller to the shift flip-flop, the system clock signal and the shift clock signal being derived from a single clock tree in the JTAG device.

15. The method of claim 14 , wherein the shift flip-flop is a negative-edge-triggered flip-flop.

16. The method of claim 10 , wherein the second cell has a shift flip-flop, and setting control data in the latch flip-flop comprises capturing the control data in the shift flip-flop of the second cell.

17. The method of claim 10 , wherein the second cell has a shift flip-flop, and setting control data in the latch flip-flop comprises shifting the control data into the shift flip-flop of the second cell through the boundary scan register.

18. The method of claim 10 , wherein the latch flip-flop in the second cell has a set or reset input terminal, and setting control data in the latch flip-flop comprises activating the set or reset input terminal.

19. The method of claim 10 , wherein the first circuit is an intellectual-property core.

20. The boundary scan circuit of claim 10 , wherein the first circuit is a flash controller and the second circuit is a flash memory.