An object of this invention is to provide a pn-varactor having a small resistance and capable of coinciding with incorporation of a circuit employing LC resonance into an integrated circuit. A dummy gate pattern 4 is formed over a n-well 1 in a semiconductor wafer and then p + diffusion regions 2, 3 are formed on both sides with the dummy gate pattern 4 as inhibition mask. For the purpose, a control voltage VT higher than potentials of the p + diffusion regions 2, 3 is applied to the n-well 1. Consequently, both the pn-junction between the n-well 1 and the p + diffusion region 2 and the pn-junction between the n-well 1 and the p + diffusion region 3 act as a pn-varactor whose capacity is changed by the control voltage VT. If an end dummy pattern is provided on both sides or around the p + diffusion regions 2, 3, imbalance in capacity due to deflection in position is prevented.
1. A pn varactor using pn junctions as variable capacitance capacitor, the pn varactor comprising:
a one-conduction-type semiconductor region arranged in a semiconductor substrate;
a first other-conduction-type semiconductor region and a second other-conduction-type semiconductor region arranged both sides of the one-conduction-type semiconductor region and constituting pn junctions together with the one-conduction-type semiconductor region;
a pseudo-gate pattern on the one-conduction-type semiconductor region;
a first dummy pattern arranged above of opposite end of the pseudo-gate pattern on the first other-conduction-type semiconductor region; and
a second dummy pattern arranged above of opposite end of the pseudo-gate pattern on the second other-conduction-type semiconductor region,
wherein the pseudo-gate pattern, the one-conduction-type semiconductor region, the first other-conduction-type semiconductor region, and the second other-conduction-type semiconductor region constitute pseudo-FET structure,
and wherein a pn junction of the one-conduction-type semiconductor region and the first other-conduction-type semiconductor region and a pn junction of the one-conduction-type semiconductor region and the second other-conduction-type semiconductor region are used as a first varactor and a second varactor, respectively, electrostatic capacitances of which vary depending on potential applied to the one-conduction-type semiconductor region.
2. A pn varactor according to claim 1 , wherein the first dummy pattern and the second dummy pattern are processed in a same manner as the pseudo-gate pattern is processed.
3. A pn varactor according to claim 1 , wherein the first dummy pattern and the second dummy pattern are obtained by processing a layer same as a layer of the pseudo-gate pattern.
4. A pn varactor according to claim 2 , wherein the first dummy pattern and the second dummy pattern are obtained by processing a layer same as a layer of the pseudo-gate pattern.
5. A pn varactor according to claim 1 , further comprising an inversion inhibiting means for inhibiting inversion of the one-conduction-type semiconductor region due to the first dummy pattern and the second dummy pattern.
6. A pn varactor using pn junctions as variable capacitance capacitor, the pn varactor comprising:
a one-conduction-type semiconductor region arranged in a semiconductor substrate and formed crosswise;
pluralities of first other-conduction-type semiconductor region and pluralities of second other-conduction-type semiconductor region arranged at portions partitioned by the one-conduction-type semiconductor region and constituting pn junctions together with the one-conduction-type semiconductor region; and
a pseudo-gate pattern formed crosswise on the one-conduction-type semiconductor region,
wherein the pseudo-gate pattern, the one-conduction-type semiconductor region, the first other-conduction-type semiconductor region, and the second other-conduction-type semiconductor region constitute pseudo-FET structure,
and wherein a pn junction of the one-conduction-type semiconductor region and the first other-conduction-type semiconductor region and a pn junction of the one-conduction-type semiconductor region and the second other-conduction-type semiconductor region are used as a first varactor and a second varactor, respectively, electrostatic capacitances of which vary depending on potential applied to the one-conduction-type semiconductor region.
7. A pn varactor according to claim 6 , wherein pluralities of the first other-conduction-type semiconductor region and pluralities of the second other-conduction-type semiconductor region are arranged in diagonal to each portion partitioned by the one-conduction-type semiconductor region.
8. A pn varactor using pn junctions as variable capacitance capacitor, the pn varactor comprising:
a one-conduction-type semiconductor region arranged in a semiconductor substrate;
a first other-conduction-type semiconductor region and a second-other-conduction-type semiconductor region arranged both sides of the one-conduction-type semiconductor region and constituting on junctions together with the one-conduction-type semiconductor region;
a pseudo-gate pattern on the one-conduction-type semiconductor region, and
a dummy pattern arranged above of entire periphery of the first other-conduction-type semiconductor region and the second other-conduction-type semiconductor region,
wherein the pseudo-gate pattern, the one-conduction-type semiconductor region, the first other-conduction-type semiconductor region, and the second other-conduction-type semiconductor region constitute pseudo-FET structure,
and wherein a pn junction of the one-conduction-type semiconductor region and the first other-conduction-type semiconductor region and a pn junction of the one-conduction-type semiconductor region and the second other-conduction-type semiconductor region are used as a first varactor and a second varactor, respectively, electrostatic capacitances of which vary depending on potential applied to the one-conduction-type semiconductor region.
9. A pn varactor according to claim 6 further comprising a dummy pattern arranged above of entire periphery of pluralities of the first other-conduction-type semiconductor region and pluralities of the second other-conduction-type semiconductor region.
10. A pn varactor according to claim 8 wherein the dummy pattern is processed in a same manner as the pseudo-gate pattern is processed.
11. A pn varactor according to claim 9 wherein the dummy pattern is processed in a same manner as the pseudo-gate pattern is processed.
12. A pn varactor according to claim 8 , wherein the dummy pattern is obtained by processing a layer same as a layer of the pseudo-gate pattern.
13. A pn varactor according to claim 9 , wherein the dummy pattern is obtained by processing a layer same as a layer of the pseudo-gate pattern.
14. A pn varactor according to claim 8 further comprising an inversion inhibiting means for inhibiting inversion of the one-conduction-type semiconductor region due to the dummy gate pattern.
15. A pn varactor according to claim 9 further comprising an inversion inhibiting means for inhibiting inversion of the one-conduction-type semiconductor region due to the dummy gate pattern.
16. A pn varactor using pn junctions as variable capacitance capacitor, the pn varactor comprising:
a one-conduction-type semiconductor region arranged in a semiconductor substrate and formed latticewise;
pluralities of first other-conduction-type semiconductor region and pluralities of second other-conduction-type semiconductor region arranged at cells partitioned by the one-conduction-type semiconductor region; and
a pseudo-pate pattern on the one-conduction-type semiconductor region,
wherein the pseudo-gate pattern, the one-conduction-type semiconductor region, the first other-conduction-type semiconductor region, and the second other-conduction-type semiconductor region constitute pseudo-FET structure,
and wherein a pn junction of the one-conduction-type semiconductor region and the first other-conduction-type semiconductor region and a pn junction of the one-conduction-type semiconductor region and the second other-conduction-type semiconductor region are used as a first varactor and a second varactor, respectively, electrostatic capacitances of which vary depending on potential applied to the one-conduction-type semiconductor region.
17. A pn varactor according to claim 16 , wherein the pluralities of the first other-conduction-type semiconductor region and pluralities of the second other-conduction-type semiconductor region are arranged alternately on each cell partitioned by the one-conduction-type semiconductor region.
18. A pn varactor using pn junctions as variable capacitance capacitor, the pn varactor comprising:
a one-conduction-type semiconductor region arranged in a semiconductor substrate;
a first other-conduction-type semiconductor region and a second other-conduction-type semiconductor region arranged both sides of the one-conduction-type semiconductor region and constituting pn junctions together with the one-conduction-type semiconductor region;
a pseudo-gate pattern on the one-conduction-type semiconductor region; and
a wiring connecting the pseudo-gate pattern and the one-conduction-type semiconductor region,
wherein the pseudo-gate pattern, the one-conduction-type semiconductor region, the first other-conduction-type semiconductor region, and the second other-conduction-type semiconductor region constitute pseudo-FET structure,
and wherein a pn junction of the one-conduction-type semiconductor region and the first other-conduction-type semiconductor region and a pn junction of the one-conduction-type semiconductor region and the second other-conduction-type semiconductor region are used as a first varactor and a second varactor, respectively, electrostatic capacitances of which vary depending on potential applied to the one-conduction-type semiconductor region.