IP Library › Granted Patent US 6,876,254
Granted Patent B2
US 6,876,254 · App. 10/406,607 · Granted Apr 5, 2005

Dual amplifier circuit and TFT display driving circuit using the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,876,254
App. No.
10/406,607
Granted
Apr 5, 2005
Kind
B2
Abstract

A method for controlling a dual-amplifier circuit, including the steps of providing an input terminal and an output terminals; providing first and second amplifiers coupled in parallel between the input terminal and the output terminal; alternately selecting one of the first and second amplifiers for use; and decreasing the amount of electrical current flowing through not-selected amplifier.

Claims (82)

1. A dual-amplifier circuit, comprising:

an input terminal to which an input signal is supplied;

an output terminal from which an output signal is supplied;

a first amplifier coupled between the input terminal and the output terminal;

a second amplifier coupled in parallel to the first amplifier between the input terminal and the output terminal;

a selecting circuit which supplies a selection signal to couple one of the first and second amplifiers alternately between the input terminal and the output terminal, wherein

each of the first and second amplifiers comprises:

1) a first supply terminal to which a first level of supply voltage is provided;

2) a second supply terminal to which a second level of supply voltage is provided; and

3) a control transistor unit, which is coupled between the first and second supply terminals and a gate of which is applied with a bias voltage,

wherein a resistance value of the control transistor unit is increased when the corresponding amplifier is not selected for use.

2. A dual-amplifier circuit, according to claim 1 , wherein the control transistor unit comprises:

1) first and second PMOS transistors, which are coupled in parallel to each other between the first and second supply terminals and each of which has a gate applied with a first bias voltage, the first and second PMOS transistors having different on-resistance values;

2) first and second NMOS transistors, which are coupled in parallel to each other between the first and second supply terminals and each of which has a gate applied with a second bias voltage, the first and second NMOS transistors having different on-resistance values; and

3) a first switch circuit, which selects one of the first and second PMOS transistors for operation in accordance with the selection signal; and

4) a second switch circuit, which selects one of the first and second NMOS transistors for operation in accordance with the selection signal.

3. A dual-amplifier circuit, according to claim 2 , wherein the control transistor unit further comprises:

1) third and fourth NMOS transistors, which are coupled in parallel to each other between the first and second supply terminals and each of which has a gate applied with the second bias voltage, the second and third NMOS transistors having different on-resistance values; and

2) a third switch circuit, which selects one of the third and fourth NMOS transistors for operation in accordance with the selection signal.

4. A dual-amplifier circuit, according to claim 1 , wherein the control transistor unit comprises:

1) a first PMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with a first bias voltage;

2) a first NMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with a second bias voltage;

3) a first resistance connected between the first supply terminal and a source of the first PMOS transistor;

4) a second resistance connected between the second supply terminal and a source of the first NMOS transistor;

5) a first switch circuit, which selectively connects the first PMOS transistor and the first resistance to the first supply terminal in accordance with the selection signal; and

6) a second switch circuit, which selectively connects the first NMOS transistor and the second resistance to the second supply terminal in accordance with the selection signal.

5. A dual-amplifier circuit, according to claim 4 , wherein the control transistor unit further comprises:

1) a third NMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with the second bias voltage;

2) a third resistance connected between the second supply terminal and a source of the third NMOS transistor; and

3) a third switch circuit, which selectively connects the third NMOS transistor and the third resistance to the second supply terminal in accordance with the selection signal.

6. A dual-amplifier circuit, according to claim 1 , wherein the control transistor unit comprises:

1) a first PMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with a first bias voltage;

2) a second PMOS transistor, which is connected in series with the first PMOS transistor and has a gate applied with the first bias voltage;

3) a first NMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with a second bias voltage;

4) a second NMOS transistor, which is connected in series with the first NMOS transistor and has a gate applied with the second bias voltage;

5) a first switch circuit, which selectively connects the first PMOS transistor and the second PMOS transistor to the first supply terminal in accordance with the selection signal; and

6) a second switch circuit, which selectively connects the first NMOS transistor and the second NMOS transistor to the second supply terminal in accordance with the selection signal.

7. A dual-amplifier circuit, according to claim 6 , wherein the control transistor unit further comprises:

1) a third NMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with the second bias voltage;

2) a fourth NMOS transistor, which is connected in series with the third NMOS transistor and has a gate applied with the second bias voltage; and

3) a third switch circuit, which selectively connects the third NMOS transistor and the fourth NMOS transistor to the second supply terminal in accordance with the selection signal.

8. A TFT display driving circuit comprising a dual-amplifier circuit according to claim 1 , which comprises:

an input terminal to which an input signal is supplied;

an output terminal from which an output signal is supplied;

a first amplifier coupled between the input terminal and the output terminal;

a second amplifier coupled in parallel to the first amplifier between the input terminal and the output terminal;

a selecting circuit which supplies a selection signal to couple one of the first and second amplifiers alternately between the input terminal and the output terminal, wherein

each of the first and second amplifiers comprises:

1) a first supply terminal to which a first level of supply voltage is provided;

2) a second supply terminal to which a second level of supply voltage is provided; and

3) a control transistor unit, which is coupled between the first and second supply terminals and a gate of which is applied with a bias voltage,

wherein a resistance value of the control transistor unit is increased when the corresponding amplifier is not selected for use.

9. A TFT display driving circuit, according to claim 8 , wherein the control transistor unit comprises:

1) first and second PMOS transistors, which are coupled in parallel to each other between the first and second supply terminals and each of which has a gate applied with a first bias voltage, the first and second PMOS transistors having different on-resistance values;

2) first and second NMOS transistors, which are coupled in parallel to each other between the first and second supply terminals and each of which has a gate applied with a second bias voltage, the first and second NMOS transistors having different on-resistance values; and

3) a first switch circuit, which selects one of the first and second PMOS transistors for operation in accordance with the selection signal; and

4) a second switch circuit, which selects one of the first and second NMOS transistors for operation in accordance with the selection signal.

10. A TFT display driving circuit, according to claim 9 , wherein the control transistor unit further comprises:

1) third and fourth NMOS transistors, which are coupled in parallel to each other between the first and second supply terminals and each of which has a gate applied with the second bias voltage, the second and third NMOS transistors having different on-resistance values; and

2) a third switch circuit, which selects one of the third and fourth NMOS transistors for operation in accordance with the selection signal.

11. A TFT display driving circuit, according to claim 8 , wherein the control transistor unit comprises:

1) a first PMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with a first bias voltage;

2) a first NMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with a second bias voltage;

3) a first resistance connected between the first supply terminal and a source of the first PMOS transistor;

4) a second resistance connected between the second supply terminal and a source of the first NMOS transistor;

5) a first switch circuit, which selectively connects the first PMOS transistor and the first resistance to the first supply terminal in accordance with the selection signal; and

6) a second switch circuit, which selectively connects the first NMOS transistor and the second resistance to the second supply terminal in accordance with the selection signal.

12. A TFT display driving circuit, according to claim 11 , wherein the control transistor unit further comprises:

1) a third NMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with the second bias voltage;

2) a third resistance connected between the second supply terminal and a source of the third NMOS transistor; and

3) a third switch circuit, which selectively connects the third NMOS transistor and the third resistance to the second supply terminal in accordance with the selection signal.

13. A TFT display driving circuit, according to claim 8 , wherein the control transistor unit comprises:

1) a first PMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with a first bias voltage;

2) a second PMOS transistor, which is connected in series with the first PMOS transistor and has a gate applied with the first bias voltage;

3) a first NMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with a second bias voltage;

4) a second NMOS transistor, which is connected in series with the first NMOS transistor and has a gate applied with the second bias voltage;

5) a first switch circuit, which selectively connects the first PMOS transistor and the second PMOS transistor to the first supply terminal in accordance with the selection signal; and

6) a second switch circuit, which selectively connects the first NMOS transistor and the second NMOS transistor to the second supply terminal in accordance with the selection signal.

14. A TFT display driving circuit, according to claim 13 , wherein the control transistor unit further comprises:

1) a third NMOS transistor, which is coupled between the first and second supply terminals and has a gate applied with the second bias voltage;

2) a fourth NMOS transistor, which is connected in series with the third NMOS transistor and has a gate applied with the second bias voltage; and

3) a third switch circuit, which selectively connects the third NMOS transistor and the fourth NMOS transistor to the second supply terminal in accordance with the selection signal.