Partitioned shifter for single instruction stream multiple data stream (SIMD) operations
View Patent ↗A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normalizer, selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed, and selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
1. A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit comprising:
providing a floating point unit with a two way aligner and a two way normalizer;
selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed; and,
selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
2. The method of claim 1 , wherein:
the floating point unit includes a floating point add unit.
3. The method of claim 1 , wherein:
the selectively aligning is performed via a partitioned shift operation.
4. The method of claim 1 , wherein:
the selectively normalizing is performed via a partitioned shift operation.
5. A floating point add unit for performing a single instruction stream multiple data stream operation and a double precision floating point operation comprising:
a first multiplexer;
a second multiplexer;
a two way aligner coupled to the first multiplexer, the two way aligner including a partitioned shift multiplexer, the partitioned shift multiplexer selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed;
an adder coupled to the two way aligner and to the second multiplexer;
a leading zero detector coupled to the adder;
a two way normalizer coupled to the leading zero detector, the two way normalizer including a partitioned shift multiplexer, the partitioned shift multiplexer selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed;
a rounder coupled to the two way normalizer; and,
a multiplexer coupled to the two way normalizer and to the rounder.
6. The floating point add unit of claim 5 , wherein:
the selectively aligning is performed via a partitioned shift operation.
7. The floating point add unit of claim 5 , wherein:
the selectively normalizing is performed via a partitioned shift operation.
8. The floating point add unit of claim 5 , wherein:
the partitioned shift multiplexer of the two way aligner includes a high byte alignment shifter and a high bit alignment shifter.
9. The floating point add unit of claim 8 , wherein:
the partitioned shift multiplexer of the two way aligner includes a low byte two way alignment shifter and a low bit two way alignment shifter, the low byte two way alignment shifter and the low bit two way alignment shifter selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
10. The floating point add unit of claim 5 , wherein:
the partitioned shift multiplexer of the two way normalizer includes a low byte shifter and a low bit shifter.
11. The floating point add unit of claim 10 , wherein:
the partitioned shift multiplexer of the two way normalizer includes a high byte two way shifter and a high bit two way shifter, the high byte two way shifter and the high bit two way shifter selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
12. The floating point add unit of claim 5 , wherein:
the partitioned shift multiplexer of the two way aligner includes a high byte alignment shifter, a high bit alignment shifter, a low byte two way alignment shifter and a low bit two way alignment shifter, the low byte two way alignment shifter and the low bit two way alignment shifter selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed; and,
the partitioned shift multiplexer of the two way normalizer includes a low byte shifter, a low bit shifter, the partitioned shift multiplexer of the two way normalizer includes a high byte two way shifter and a high bit two way shifter, the high byte two way shifter and the high bit two way shifter selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
13. A floating point unit for performing a single instruction stream multiple data stream operation and a double precision floating point operation comprising:
a first multiplexer;
a second multiplexer;
a two way aligner coupled to the first multiplexer, the two way aligner including a partitioned shift multiplexer, the partitioned shift multiplexer selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed;
an adder coupled to the two way aligner and to the second multiplexer;
a leading zero detector coupled to the adder;
a two way normalizer coupled to the leading zero detector, the two way normalizer including a partitioned shift multiplexer, the partitioned shift multiplexer selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed;
a rounder coupled to the two way normalizer; and,
a multiplexer coupled to the two way normalizer and to the rounder.
14. The floating point unit of claim 13 , wherein:
the selectively aligning is performed via a partitioned shift operation.
15. The floating point unit of claim 13 , wherein:
the selectively normalizing is performed via a partitioned shift operation.
16. The floating point unit of claim 13 , wherein:
the partitioned shift multiplexer of the two way aligner includes a high byte alignment shifter and a high bit alignment shifter.
17. The floating point unit of claim 16 , wherein:
the partitioned shift multiplexer of the two way aligner includes a low byte two way alignment shifter and a low bit two way alignment shifter, the low byte two way alignment shifter and the low bit two way alignment shifter selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
18. The floating point unit of claim 13 , wherein:
the partitioned shift multiplexer of the two way normalizer includes a low byte shifter and a low bit shifter.
19. The floating point unit of claim 18 , wherein:
the partitioned shift multiplexer of the two way normalizer includes a high byte two way shifter and a high bit two way shifter, the high byte two way shifter and the high bit two way shifter selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
20. The floating point unit of claim 13 , wherein:
the partitioned shift multiplexer of the two way aligner includes a high byte alignment shifter, a high bit alignment shifter, a low byte two way alignment shifter and a low bit two way alignment shifter, the low byte two way alignment shifter and the low bit two way alignment shifter selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed; and,
the partitioned shift multiplexer of the two way normalizer includes a low byte shifter, a low bit shifter, the partitioned shift multiplexer of the two way normalizer includes a high byte two way shifter and a high bit two way shifter, the high byte two way shifter and the high bit two way shifter selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.