Wafer alignment mark for image processing including rectangular patterns, image processing alignment method and method of manufacturing semiconductor device
View Patent ↗An alignment mark is arranged to be within an image screen and the alignment mark is formed with rectangular patterns having varied dimensions from each other. The signal waveforms from each of the rectangular patterns are measured. The number of the rectangular patterns with normal waveforms is compared to the minimum required number of marks prescribed beforehand. The amount of deviation in alignment is calculated by excluding the abnormal measured result.
1. A wafer alignment mark for image processing, comprising:
a plurality of rectangular patterns provided in the wafer alignment mark,
wherein the wafer alignment mark is disposed near a peripheral edge within a range of a shot to be picked up, and
wherein the plurality of rectangular patterns are formed smaller than the wafer alignment mark and comprise different dimensions from each other.
2. The wafer alignment mark for image processing according to claim 1 , wherein the wafer alignment mark is disposed in a scribe region provided in the peripheral edge of the one shot.
3. The wafer alignment mark for image processing according to claim 1 , wherein the wafer alignment mark is disposed at least in one axial direction out of two axial directions crossing each other at right angles in the one shot.
4. The wafer alignment mark for image processing according to claim 1 , wherein the rectangular patterns comprise frame-type patterns comprising a plurality of lines in a frame form.
5. The wafer alignment mark for image processing according to claim 4 , wherein the plurality of lines comprise varied widths and the frame-type patterns comprise similar shapes.
6. The wafer alignment mark for image processing according to claim 4 , wherein the rectangular patterns comprise varied ratios of line width to line length and the frame-type patterns comprise similar shapes.
7. The wafer alignment mark for image processing according to claim 4 , wherein:
the rectangular patterns comprise frame-type patterns with different line length ratios; and
the rectangular patterns are disposed in the one shot by varying facing directions of the frame-type patterns.
8. The wafer alignment mark for image processing according to claim 1 , wherein the rectangular patterns comprise box-type patterns having rectangular external shapes.
9. The wafer alignment mark for image processing according to claim 8 , wherein the rectangular patterns comprise varied lengths of sides which form the external shapes of the box-type patterns and comprise similar shapes.
10. The wafer alignment mark for image processing according to claim 1 , wherein the rectangular patterns are arranged in accordance with an order of a ratio of change in dimensions of the rectangular patterns.
11. The wafer alignment mark for image processing according to claim 1 , wherein the rectangular patterns are arranged at random regardless of a ratio of change in dimensions of the rectangular patterns.
12. The wafer alignment mark for image processing according to claim 1 , wherein each of said plurality of rectangular patterns comprises individual dimensions that are different from dimensions of other rectangular patterns.
13. The wafer alignment mark for image processing according to claim 1 , wherein each of said plurality of rectangular patterns comprises four sides, each side having a length,
wherein the length of each side is between 1 μm and 3 μm.
14. The wafer alignment mark for image processing according to claim 1 , wherein each of said plurality of rectangular patterns comprises four sides, each side having a width,
wherein the widths of each side of each rectangular pattern are different from the widths of each side of the other rectangular patterns.
15. A semiconductor device wafer comprising:
a plurality of shots disposed along a surface of the wafer;
at least one wafer alignment mark disposed along a peripheral edge of a shot in said plurality of shots; and
a plurality of rectangular patterns provided in the at least one wafer alignment mark,
wherein the plurality of rectangular patterns are formed smaller than the wafer alignment mark and comprise different dimensions from each other.
16. The semiconductor device according to claim 15 , wherein the at least one wafer alignment mark is disposed in at least one axial direction out of two axial directions crossing each other at right angles in each of said plurality of shots.
17. The semiconductor device according to claim 15 , wherein the at least one wafer alignment mark comprises a plurality of wafer alignment marks.
18. The semiconductor device according to claim 17 , wherein the plurality of wafer alignment marks are disposed in each of two axial directions crossing each other at right angles in each of said plurality of shots.
19. The semiconductor device according to claim 15 , wherein the at least one wafer alignment mark is disposed in a scribe region provided in the peripheral edge of each of said plurality of shots.