Memory system and method of using same
View Patent ↗A memory system and method of using same are provided. In one embodiment of the present invention, the memory system may include a plurality of logic sections that may be used to facilitate execution of relatively complex atomic read-modify-write operations.
1. A memory system, comprising:
at least one memory region adapted to store data; and
a logic section adapted to be used to execute an atomic operation during a data transfer cycle of the memory system, the atomic operation including performing an addition operation involving summing together a first complete data word from the memory region and a second complete data word from a device external to the memory system, the first complete data word being retrieved from the memory region and being received by the logic section during the data transfer cycle, and the second complete data word being received by the logic section from the device during the data transfer cycle, the atomic operation also including transmitting to the device the first complete data word.
2. The memory system of claim 1 , wherein the memory system comprises a plurality of memory regions and a plurality of logic sections, each of the logic sections being associated with a respective one of the memory regions.
3. The memory system of claim 2 , wherein the memory system comprises at least one electrical circuit, board, and the memory regions and logic sections are comprised in the at least one electrical circuit board.
4. A memory system, comprising:
at least one memory region adapted to store data; and
a logic section adapted to be used to execute an atomic operation during a data transfer cycle of the memory system, the atomic operation including performing a plurality of arithmetic operations involving portions of a first data word from the memory region and portions of a second data word from a device external to the memory system, the portions of the first data word being retrieved from the memory region and being received by the logic section during the data transfer cycle, and the portions of the second data word being received by the logic section from the device during the data transfer cycle, the atomic operation also including transmitting to the device the portions of the first data word.
5. A method of using a memory system, the method comprising:
executing, using a logic section comprised in the memory system, an atomic operation during a data transfer cycle of the memory system, the atomic operation including performing an addition operation involving summing together a first complete data word from a memory region comprised in the memory system and a second complete data word from a device external to the memory system, the first complete data word being retrieved from the memory region and being received by the logic section during the data transfer cycle, the second complete data word being received by the logic section from the device during the data transfer cycle, the atomic operation also including transmitting to the device the first complete data word.
6. The method of claim 5 , wherein the memory system comprises a plurality of memory regions and a plurality of logic sections, each of the logic sections being associated with a respective one of the memory regions.
7. The method of claim 5 , wherein the memory system comprises at least one electrical circuit board, and the memory regions and logic sections are comprised in the at least one electrical circuit board.
8. A method of using a memory system, the method comprising:
executing, using a logic section, an atomic operation during a data transfer cycle of the memory system, the atomic operation including performing a plurality of arithmetic operations involving portions of a first data word from a memory region comprised in the memory system and portions of a second data word from a device external to the memory system, the portions of the first data word being retrieved from the memory region and being received by the logic section during the data transfer cycle, and the portions of the second data word being received by the logic section from the device during the data transfer cycle, the atomic operation also including transmitting to the device the portions of the first data word.