Self-configuring distributed switch

1. A mechanism for enabling an interleaving of time-critical type-1 and delay-tolerant type-2 packets on a shared channel in a communication module having a local time counter, the module transmitting type-1 and type-2 data packet streams on a shared channel, the mechanism comprising:

a type-1 packet buffer;

a type-2 packet buffer;

a register for storing a transfer duration of a packet waiting in the type-2 packet buffer, the transfer duration being represented by an integer X≧0;

an integer value produced from the output of a time counter;

a comparator for comparing said integer value of the time counter and the transfer duration and producing a two-bit output Q, the output Q being “00” if transfer duration is smaller than the integer value of the time counter, and “11” if the integer value of the time counter is zero, regardless of the value of the transfer duration; and

a 2:1 selector for selecting a packet from the type-1 packet register if Q is “11”, the type-2 packet register if Q is “10”, and remaining in an idle state if Q is “00”.

2. The mechanism as claimed in claim 1 wherein the time counter is an up-counter, the counter period is a power of 2, and the integer value is derived by reversing each bit in an output of the up-counter.

3. A method of interleaving time-critical data packets and delay-tolerant data packets on a shared channel emanating from a control port of a first switching node, while meeting a strict time requirement for transmission of time-critical data packets, comprising steps of:

storing said delay-tolerant data packets in a payload packet buffer associated with said control port;

determining a transfer duration for a delay-tolerant data packet to be transferred from the payload packet buffer;

determining a current local time;

determining a time interval before a next one of the time-critical data packets must be transferred from the control port;

transferring the delay tolerant data packet if the transfer duration does not exceed the time interval before the next one of the time-critical data packets must be transferred from the control port; otherwise

disabling transfer of the delay-tolerant data packet in said payload packet buffer until the next one of the time-critical packets is transferred from the control port.

4. The method as claimed in claim 3 wherein the step of determining the current local time further comprises a step of reading a clock-driven cyclic time counter, and the step of determining the time interval further comprises a step of checking a time-critical data packet buffer to determine whether there is a time-critical data packet waiting to be transferred.

5. The method as claimed in claim 4 wherein said cyclic time counter has a period that comprises a power of 2 multiple of a clock period, and the step of transferring the time-critical data packet is performed when the cyclic time counter reads zero.

6. The method as claimed in claim 5 wherein determining said transfer duration further comprises a step of storing the transfer duration in a transfer duration indicator.

7. The method as claimed in claim 6 wherein said time-critical packets include timing packets and control packets, and the method further comprises a step of inserting a time indicator into each timing packet before said each timing packet is transferred.

8. The method as claimed in claim 7 further comprising a step of setting a period of the cyclic time counter so that it exceeds a propagation delay from said first switching module to a second switching module.

9. The method as claimed in claim 7 further comprising a step of setting a period of said cyclic time counter so that it exceeds a sum of a transfer duration of any of said delay-tolerant data packets plus a time required to transfer any of said time-critical data packets.

10. A control circuit for enabling interleaving time-critical data packets and delay-tolerant data packets on a shared channel emanating from a communication, the control circuit comprising:

a timing-packet register for storing a time-critical data packet;

a payload packet buffer for storing delay-tolerant data packets;

a first register for storing a reading of a local time counter;

a second register for storing a transfer duration period of a next delay-tolerant data packet to be transferred from the payload packet buffer;

a comparator for comparing the contents of the first register and the second register; and

a selector for selecting a packet from one of the timing packet register and the payload packet buffer, depending on an output of the comparator.

11. The control circuit as claimed in claim 10 further adapted to select the time-critical data packet from the timing packet register at specific instants indicated by the output of the comparator.

12. The control circuit as claimed in claim 11 wherein the local time counter comprises a clock-driven down-counter.

13. The control circuit as claimed in claim 12 wherein the local time counter is C-bits wide, wherein C>1, and each zero reading of the first register causes the comparator to output an indicator that the time-critical packet must be transferred.

14. The control circuit as claimed in claim 13 wherein a sum of a time required to transfer any delay-tolerant data packet, plus a time required to transfer any packet in the timing packet register, does not exceed an interval between two successive zero readings of the local time counter.

15. The control circuit as claimed in claim 14 wherein the comparator is adapted to output one of three values, comprising:

“00” if a value stored in the first register is smaller than a value stored in the second register;

“10” if the value stored in the first register is not smaller than the value stored in the second register; and

“11” if the value stored in the first register is zero.

16. The control circuit as claimed in claim 15 wherein said selector is adapted to:

transfer a packet from the timing packet register if the output of the comparator equals ‘11’;

transfer a packet from the payload packet buffer if the output of the comparator equals ‘10’; and

remain idle if the output of the comparator equals ‘00’.