Integrated circuit and method for detecting the state of an oscillating signal

1. An integrated circuit, comprising:

circuit elements configured to be clocked via an oscillating signal; and

a detector configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal, wherein the detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal and a second delay line configured to provide a second delayed signal to the logic, wherein the first delayed signal and the second delayed signal oscillate at the same frequency as the oscillating signal and the logic is configured to receive at least one high level signal and at least one low level signal and indicate the oscillating signal is oscillating.

2. The integrated circuit of claim 1 , wherein the oscillating signal is provided to the logic and signal levels in the oscillating signal overlap similar signal levels in the first delayed signal and similar signal levels in the second delayed signal.

3. An integrated circuit, comprising:

circuit elements configured to be clocked via an oscillating signal; and

a detector configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal, wherein the detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal and a second delay line configured to provide a second delayed signal to the logic, wherein the first delayed signal and the second delayed signal oscillate at the same frequency as the oscillating signal and the logic is configured to receive similar signal levels and indicate the oscillating signal is stopped.

4. The integrated circuit of claim 1 , wherein the first delay line is a fixed delay line.

5. The integrated circuit of claim 1 , wherein the first delay line is a variable delay line.

6. The integrated circuit of claim 1 , further comprising an adjustment circuit configured to indicate that the first delay line is set to a first delay value to detect the stale of the oscillating signal.

7. The integrated circuit of claim 1 , wherein the first and second delay lines are variable delay lines.

8. The integrated circuit of claim 7 , further comprising an adjustment circuit configured to indicate the first and second delay lines are set to first and second delay values to detect the state of the oscillating signal.

9. The integrated circuit of claim 1 , further comprising a distribution circuit configured to distribute the detection signal to disable pulse width modulator outputs.

10. The integrated circuit of claim 1 , further comprising a distribution circuit configured to distribute the detection signal indicating the oscillating signal is stopped by providing an unsynchronized reset signal to circuit elements in the integrated circuits.

11. The integrated circuit of claim 1 , further comprising a distribution circuit configured to distribute the detection signal indicating the oscillating signal is stopped by providing a reset signal to synchronized circuit elements in the integrated circuit.

12. The integrated circuit of claim 1 , further comprising a distribution circuit configured to distribute the detection signal indicating the oscillating signal is stopped by providing a reset signal to an input/output circuit.

13. An integrated circuit, comprising:

a circuit element configured to be clocked by a first oscillating signal; and

a first detector configured to detect a state of a second oscillating signal and provide a first detection signal indicating the state of the second oscillating signal, wherein the first detector is configured to sample the second oscillating signal at a sampling rate derived from the first oscillating signal and comprises a first circuit configured to receive and sample the second oscillating signal via the first oscillating signal to obtain a first result and to provide the first result to detection logic and a second circuit configured to receive and sample the first result via the first oscillating signal to obtain a second result and to provide the second result to the detection logic.

14. An integrated circuit, comprising:

a circuit element configured to be clocked by a first oscillating signal; and

a first detector configured to detect a state of a second oscillating signal and provide a first detection signal indicating the state of the second oscillating signal, wherein the first detector is configured to sample the second oscillating signal at a sampling rate derived from the first oscillating signal; and

a second detector configured to detect a state of a third oscillating signal and provide a second detection signal indicating the state of the third oscillating signal, wherein the first oscillating signal is divided to obtain the third oscillating signal and the second detector is configured to sample the third oscillating signal at a sampling rate derived from the second oscillating signal.

15. The integrated circuit of claim 13 , wherein the detection logic is configured to receive similar signals and indicate the second oscillating signal is stopped.

16. A method for detecting a state of an oscillating signal, comprising:

providing the oscillating signal to detection logic;

providing the oscillating signal to a first delay line;

obtaining a first delayed signal from the first delay line;

providing the first delayed signal to the detection logic;

providing the first delayed signal to a second delay line;

obtaining a second delayed signal from the second delay line;

providing the second delayed signal to the detection logic; and

receiving a high signal level and a low signal level at the detection logic and indicating the oscillating signal is oscillating.

17. The method of claim 16 , wherein the oscillating signal includes signal levels that overlap similar signal levels in the first delayed signal and similar signal levels in the second delayed signal.

18. The method of claim 16 , further comprising:

receiving identical signal levels at the detection logic and indicating the oscillating signal is stopped.

19. The method of claim 16 , further comprising:

adjusting a delay value of the first delay line; and

indicating the delay value detects the state of the oscillating signal.