High reliability memory module with a fault tolerant address and command bus
View Patent ↗A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit, a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
1. A dual in-line memory module (DIMM) comprising:
a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length,
a first plurality of connector locations on said first side extending along a first edge of said board that extends the length of the board;
a second plurality of connector locations on said second side extending on said first edge of said board;
a locating key having its center positioned on said first edge and located between 82 mm and 86 mm from said first end of said board and located between 66 and 70 mm from said second end of said board.
2. The DIMM of claim 1 wherein there is further provided on said first side multiple dynamic random access memories (DRAMs):
a phase lock loop circuit; and
a 28 bit 1 to 2 register circuit having error correction code (EGG) across data inputs and a real time error line for reporting both correctable errors and uncorrectable error conditions mounted on said first side of said board.
3. The DIMM of claim 1 wherein said multiple DRAMs are mounted on said first side of said printed circuit board.
4. The DIMM of claim 1 wherein said multiple DRAMs are mounted on said second side of said printed circuit board.
5. The memory module of claim 1 wherein the output pins of said multiple DRAMS are connected to selected ones of said connector locations on said board.
6. The memory module of claim 1 wherein the first edge of the first side of said board has one hundred and thirty-eight (138) connector locations and an identical plurality of connector locations on the said first edge of said second side of said board for a total of two hundred and seventy-six (276) contacts on said board.
7. The memory module of claim 1 wherein selected contacts on said first side surface are coupled to selected contacts on said second side to provide redundant contacts for selected signals sent to and received from said DRAMs, said register chip, said EE PROM and/or said phase locked loop.
8. The dual in-line memory module of claim 1 wherein;
a selected number of said contacts on said first side are commonly connected to a selected number of contacts on said second side to provide said board with a selected number of redundant contacts;
a plurality of dynamic random access memory chips on said first and second sides; a 2 or 32K bit serial EE PROM and a 28 bit, 1 to 2 register circuit chip having error correction code (ECC), a multi-byte fault reporting register, read via an independent bus, and real time error lines for both correctable errors and uncorrectable error conditions on said first side; and
a phase lock loop circuit coupled to said plurality of dynamic random access memory chips on said first and second sides and to said register chip on said first side.
9. The dual in-line memory module of claim 1 wherein;
a selected number of said contacts on said first side are commonly connected to a selected number of contacts on said second side to provide said board with a selected number of redundant contacts;
a plurality of dynamic random access memory chips on said first and second sides;
a 2 or 32K bit serial EE PROM and a 28 bit, 1 to 2 register circuit chip having parity checking, a multi-byte fault reporting register, read via an independent bus, and real time error lines for both correctable errors and uncorrectable error conditions on said first side; and
a phase lock loop circuit coupled to said plurality of dynamic random access memory chips on said first and second sides and to said register chip on said first side.
10. The memory module of claim 1 wherein selected contacts CS 1 , CKE 0 , CKE 1 , RAS, CAS, WE, CK 0 and CK 0 B are positioned at selected nominal distances from the key on said first edge of said DIMM as follows:
NOMINAL
DIRECTION
DISTANCE
FROM
CONTACT or
SIDE of
FROM CENTER
CENTER
SIGNAL
PIN#
DIMM
OF KEY
OF KEY
CS0
86
FRONT
11.495 mm
RIGHT
CS0
224
BACK
11.495 mm
LEFT
CS1
91
FRONT
16.495 mm
RIGHT
CS1
229
BACK
16.495 mm
LEFT
CKE0
65
FRONT
13.505 mm
LEFT
CKE0
203
BACK
13.505 mm
RIGHT
CKE1
62
FRONT
16.505 mm
LEFT
CKE1
200
BACK
16.505 mm
RIGHT
RAS
222
BACK
9.495 mm
LEFT
CAS
87
FRONT
12.495 mm
RIGHT
WE
84
FRONT
9.495 mm
RIGHT
CK0
77
FRONT
2.495 mm
RIGHT
CK0
215
BACK
2.495 mm
LEFT
CK0B
78
FRONT
3.495 mm
RIGHT
CK0B
216
BACK
3.495 mm
LEFT.
11. The DIMM of claim 1 wherein there is further provided on said first side multiple dynamic random access memories (DRAMs):
a phase lock loop circuit; and
a 28 bit 1 to 2 register circuit having error correction code (ECC) across data inputs, parity checking, and a real time error line for reporting both correctable errors and uncorrectable error conditions mounted on said first side of said board.
12. The DIMM of claim 11 wherein there are 22 data inputs to the register ECC circuitry.