Electrical line end shortening quantification
View Patent ↗The present invention enables the quantification of line end shortening by utilizing a pattern of multiple conductive paths, each conductive path can include a conductor at each end, each conductor connected to a separate contact with the contacts connected by a polysilicon conductor. The conductors can vary in length by a constant increment from conductive path to conductive path, beginning with a length that results in a significant overlap at the contacts to a length that results in a significant underlap at the contacts. Resistance measurements of each conductive path can be made until a change either to or from an “open” occurs; this is the point from which, using the constant increment, the LES can be characterized.
1. A method for preparing a semiconductor substrate for use in characterizing line end shortening associated with integrated circuit fabrication, the method comprising:
providing on the semiconductor substrate a plurality of conductive paths which each has at least one contact portion;
for each of said conductive paths, designing an associated line end structure corresponding to an integrated circuit design, including designing each said line end structure such that, when provided on the semiconductor substrate, the line end structure is expected to contact only a predetermined amount of the contact portion of the associated conductive path, wherein the predetermined amount associated with each said line end structure differs from the predetermined amount associated with each remaining said line end structure;
providing the line end structures on the semiconductor substrate;
sequentially measuring conductivity between each of said conductive paths and the associated line end structure; and
calculating line end shortening according to a change of measured conductivity between at least two sequential conductivity measurements, wherein at least one of the at least two sequential conductivity measurements includes a measurement of a substantially open-circuit.
2. The method of claim 1 wherein the predetermined amount associated with each said line end structure differs from the predetermined amounts associated with each remaining said line end structure by respective multiples of a predetermined difference amount.
3. The method of claim 2 wherein the predetermined difference amount is 10 nanometers.
4. The method of claim 1 wherein said providing step includes providing a further said conductive path, and said designing step includes designing a further said line end structure such that, when provided on the semiconductor substrate, said further line end structure is not expected to contact the contact portion of the further conductive path.
5. The method of claim 1 wherein the predetermined amount associated with one of said line end structures is 100 nanometers.
6. The method of claim 5 wherein said providing step includes providing a further said conductive path, and said designing step includes designing a further said line end structure such that, when provided on the semiconductor substrate, said further line end structure is expected to be separated from the contact portion of the further conductive path by 50 nanometers.
7. The method of claim 1 wherein said plurality of conductive paths are all of substantially equal length.
8. The method of claim 1 wherein said plurality of conductive paths are of mutually differing lengths.
9. An apparatus for use in characterizing line end shortening associated with integrated circuit fabrication, comprising:
a semiconductor substrate;
a plurality of conductive paths provided on said semiconductor substrate, each of said conductive paths having a contact portion; and
a plurality of line end structures provided on said semiconductor substrate and corresponding to an integrated circuit design, said line end structures respectively associated with said conductive paths, each said line end structure having been designed such that, when provided on the semiconductor substrate, the line end structure is expected to contact only a predetermined amount of the contact portion of the associated conductive path, at least one said line end structure contacting the contact portion of the associated conductive path, and wherein the predetermined amount associated with each said line end structure differs from the predetermined amount associated with each remaining said line end structure, the apparatus configured to sequentially measure conductivity between each of said conductive paths and the associated line end structure, and to calculate line end shortening according to a change of measured conductivity between at least two sequential conductivity measurements, wherein at least one of the at least two sequential conductivity measurements includes a measurement of a substantially open-circuit.
10. The apparatus of claim 9 wherein the predetermined amount associated with each said line end structure differs from the predetermined amounts associated with each remaining said line end structure by respective multiples of a predetermined difference amount.
11. The apparatus of claim 10 wherein the predetermined difference amount is 10 nanometers.
12. The apparatus of claim 9 wherein one of said line end structures is separated from the contact portion of the associated conductive path.
13. The apparatus of claim 9 wherein the predetermined amount associated with one of said line end structures is 100 nanometers.
14. The apparatus of claim 9 wherein said plurality of conductive paths are all of substantially equal length.
15. The apparatus of claim 9 wherein said plurality of conductive paths are of mutually differing lengths.