Circuitry to provide a low power input buffer
View Patent ↗Input buffer circuitry that prevents high voltage output from high voltage circuitry from being applied to connected low voltage circuitry. An input of the input buffer circuitry receives signals from the high voltage circuitry. Pinch-off circuitry receives the input signals and prevents voltage above a threshold voltage from being applied to an output of the pinch-off circuitry. Boost circuitry controls the threshold voltage of the pinch-off circuitry and pull-up circuitry draws voltage from the output of the pinch-off circuitry to regulate the control by the booster circuitry.
1. An input buffer circuitry that connects low power circuitry to high power circuitry wherein said low power circuitry operates at first voltage and said high power circuitry operates at a second voltage that is greater than said first voltage comprising:
an input that receives signals at said second voltage from said high power circuitry;
pinch-off circuitry that receives said signals and prevents voltage above a threshold voltage from being applied to an output of said pinch-off circuitry wherein said pinch-off circuitry includes a first pinch-off transistor and a second pinch-off transistor and wherein said first pinch-off transistor and said second pinch-off transistor are n-channel transistors;
boost circuitry that controls said threshold voltage of said pinch-off circuitry; and
pull-up circuitry that connects to said output of said pinch-off circuitry to draw current from said output of said pinch-off circuitry.
2. The input buffer circuitry of claim 1 wherein said pull-up circuitry is connected to said boost circuitry to regulate control of said threshold voltage from said current drawn by said pull-up circuitry.
3. The input buffer of claim 1 wherein said pinch-off circuitry comprises:
a pinch-off transistor.
4. The input buffer circuitry of claim 3 wherein said pinch-off transistor is an N-channel transistor.
5. The input buffer circuitry of claim 3 further comprising:
a source of said pinch-off transistor connected to said input;
a drain of said pinch-off circuit connected to buffer circuitry and said pull-up circuitry; and
a gate of said pinch-off transistor connected to said boost circuitry.
6. The input buffer circuitry of claim 5 wherein said boost circuitry is a pull-up transistor.
7. The input buffer circuitry of claim 6 wherein said pull-up transistor is a P-channel transistor.
8. The input buffer circuitry of claim 6 further comprising:
a source of said pull-up transistor connected to a power supply;
a drain of said pull-up transistor connected to said gate of said pinch-off transistor; and
a gate of said pull-up transistor is connected to ground.
9. The input buffer circuitry of claim 8 said power supply is 3.3 volts.
10. The input buffer circuitry of claim 8 wherein said pull-up circuitry comprises:
a bootstrap capacitor.
11. The input buffer circuitry of claim 9 further comprising:
an input of said bootstrap capacitor connected to said drain of said pinch-off capacitor; and
an output of said bootstrap capacitor connected to said drain of said pull-up transistor.
12. The input buffer circuitry of claim 1 further comprising:
a source of said first pinch-off transistor connected to said input;
a drain of said first pinch-off circuit connected to buffer circuitry and said pull-up circuitry;
a gate of said first pinch-off transistor connected to said boost circuitry;
a source of said second pinch-off transistor connected to said input;
a drain of said second pinch-off circuit connected to buffer circuitry and said pull-up circuitry; and
a gate of said second pinch-off transistor connected to a power supply.
13. The input buffer circuitry of claim 12 wherein said boost circuitry comprises:
a pull-up transistor.
14. The input buffer circuitry of claim 12 wherein said pull-up transistor is a P-channel transistor.
15. The input buffer circuitry of claim 12 further comprising:
a source of said pull-up transistor connected to said power supply; and
a drain of said pull-up transistor connected to said gate of said first pinch-off transistor.
16. The input buffer circuitry of claim 15 wherein said pull-up circuitry comprises:
a first reverse bias diode; and
a second reverse bias diode.
17. The input buffer circuitry of claim 16 wherein said first reverse bias diode comprises a first reverse bias diode transistor and said second reverse bias diode comprises a second reverse bias diode transistor.
18. The input buffer circuitry of claim 17 wherein said first reverse bias diode transistor and said second reverse bias diode transistor are N-channel transistors.
19. The input buffer circuitry of claim 17 further comprising:
a source of said first reverse bias diode transistor connected to said drain of said first pinch-off transistor and said drain of said second pinch-off transistor;
a drain of said first reverse bias diode transistor connected to a source of said second reverse bias diode transistor;
a gate of said first reverse bias diode transistor connected to said drain of said first pinch-off transistor and said drain of said second pinch-off transistor;
a drain of said second pinch-off transistor connected to said gate and said drain of said pull-up transistor and said gate of said first pinch-off transistor; and
a gate of said second pinch-off transistor connected to said gate and said drain of said pull-up transistor and said gate of said first pinch-off transistor.