Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory
View Patent ↗Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.
1. A semiconductor device comprising a nonvolatile memory array and a central processing unit,
wherein said nonvolatile memory array comprises a plurality of memory cells, a plurality of word lines, a plurality of data lines, and a control circuit,
wherein each of said memory cells comprises a gate terminal, a first terminal and a second terminal,
wherein each of said word lines is coupled to the gate terminals of corresponding ones of said memory cells,
wherein each of said data lines is coupled to the first terminals of corresponding ones of said memory cells,
wherein said central processing unit is capable of instructing a program operation to said nonvolatile memory array, and
wherein in said program operation, said control circuit of said nonvolatile memory array selects one word line, supplies a program voltage to the selected word line, and supplies a first voltage for a first duration of time to a first data line coupled to a first memory cell to be subjected to programming, and supplies the first voltage for a second duration of time to a second data line coupled to a second memory cell to be subjected to programming after the start of supplying the first voltage to the first data line and before the completion of the first duration of time, regardless of whether one or more memory cells not to be subjected to programming are coupled to the selected word line between the first memory cell and the second memory cell.
2. A semiconductor device according to claim 1 ,
wherein said first duration of time is shorter than said second duration of time.
3. A semiconductor device according to claim 2 ,
wherein said nonvolatile memory array receives a clock signal, and
wherein said first duration of time and said second duration of time are based on said clock signal.
4. A semiconductor device according to claim 1 ,
wherein said central processing unit is further capable of instructing a verify operation to said nonvolatile memory array.
5. A semiconductor device according to claim 4 ,
wherein said control circuit of said nonvolatile memory array is capable of conducting another program operation when it is found by said verify operation that programming of one or more memory cells is not completed.
6. A semiconductor device according to claim 1 ,
wherein said nonvolatile memory array comprises a data buffer including a plurality of buffer cells, and
wherein said data buffer is capable of storing data for programming to said memory cells.
7. A semiconductor device according to claim 6 ,
wherein each of said buffer cells is coupled to a corresponding data line and is capable of storing one of a first state and a second state,
wherein for a memory cell to be subjected to programming, a corresponding buffer cell has said first state stored therein, and
wherein for a memory cell not to be subjected to programming, a corresponding buffer cell has said second state stored therein.
8. A semiconductor device according to claim 1 ,
wherein said second terminals of respective memory cells coupled to a same word line are coupled to each other.
9. A semiconductor device according to claim 1 ,
wherein said memory cells to be subjected to programming include said first memory cell, said second memory cell and a third memory cell,
wherein said one or more memory cells not to be subjected to programming include a fourth memory cell,
wherein said third memory cell is arranged next to said second memory cell and said fourth memory cell is arranged between said first memory cell and said second memory cell, and
wherein a supply of said first voltage to a third the data line coupled to said third memory cell is started after said supply of said first voltage to said second data line coupled to said second memory cell is started.