Directory-based cache coherency scheme for reducing memory bandwidth loss

1. A memory system employing a directory-based cache coherency scheme, the memory system comprising:

a memory unit comprising a plurality of memory modules, each memory module storing a plurality of cache lines, with each cache line comprising a plurality of data bits and a plurality of informational bits;

a common data bus coupled to all of the memory modules and configured to read/write data bits from/to all of the memory modules;

a plurality of information buses, each information bus coupled to a corresponding one of the memory modules and configured to read/write informational bits of cache lines from/to its corresponding memory module; and

a memory controller controlling access to the memory unit, the memory controller configured to read a plurality of data bits and a plurality of information bits of a first cache line from a first memory module via the common data bus and the information bus corresponding to the first memory module, and in a parallel operation to write a plurality of informational bits of a second cache line to a second memory module via the information bus corresponding to the second memory module.

2. The memory system of claim 1 , wherein the plurality of informational bits of each cache line comprises:

directory tag bits.

3. The memory system of claim 1 , wherein the plurality of informational bits of each cache line comprises:

error correction code (ECC) bits.

4. The memory system of claim 1 wherein the memory unit comprises a plurality of dual in-line memory modules (DIMMs).

5. The memory system of claim 4 , wherein each DIMM comprises:

a plurality of random access memory (RAM) devices.

6. The memory system of claim 5 , wherein the plurality of RAM devices further comprises:

a sub-plurality of RAM devices for storing data bits;

a sub-plurality of RAM devices for storing ECC bits;

a sub-plurality of RAM devices for storing directory tag bits.

7. The memory system of claim 1 , further comprising:

an address/control bus coupled between each of the memory modules and the controller.

8. The memory system of claim 7 , wherein the address/control bus comprises:

a plurality of ECC/tag control lines, one coupled to each memory module; wherein a ECC/tag control line is configured to enable/disable the ability of ECC and directory tag bits to be written to its corresponding memory module.

9. A computer system comprising:

a system bus;

a microprocessor coupled to the system bus and including a cache memory; and

a main memory system employing a directory-based cache coherency scheme coupled to the system bus, configured to store a plurality of cache lines, and configured to transfer to and from the cache memory a plurality of cache lines requested by the microprocessor, the main memory system comprising:

a memory unit comprising a plurality of memory modules, each memory module storing a plurality of cache lines, each cache line comprising a plurality of data bits and a plurality of informational bits;

a common data bus coupled to all of the memory modules and configured to read/write data bits from/to all of the memory modules;

a plurality of information buses, each information bus coupled to a corresponding one of the memory modules and configured to read/write informational bits of cache lines from/to its corresponding memory module; and

a memory controller controlling access to the memory unit, the memory controller configured to read a plurality of data bits and a plurality of informational bits of a first requested cache line from a first memory module via the common data bus and the information bus corresponding to the first memory module, and in a parallel operation to write a plurality of informational bits of a second requested cache line to a second memory module via the information bus corresponding to the second memory module.

10. The computer system of claim 9 , wherein the plurality of informational bits of each cache line comprises:

directory tag bits.

11. The computer system of claim 9 , wherein the plurality of informational bits of each cache line comprises:

error correction code (ECC) bits.

12. The computer system of claim 9 wherein the memory unit comprises a plurality of dual in-line memory modules (DIMMs).

13. The computer system of claim 12 , wherein each DIMM comprises:

a plurality of random access memory (RAM) devices.

14. The computer system of claim 13 , wherein the plurality of RAM modules further comprises:

a sub-plurality of RAM devices for storing data bits;

a sub-plurality of RAM devices for storing ECC bits;

a sub-plurality of RAM devices for storing directory tag bits.

15. The computer system of claim 9 , further comprising:

an address/control bus coupled between each of the memory modules and the controller.

16. The computer system of claim 15 , wherein the address/control bus comprises:

a plurality of ECC/tag control lines, one coupled to each memory module; wherein each ECC/tag control line is configured to enable/disable the ability of ECC and directory tag bits to be written to its corresponding memory module.

17. A method of updating a tag directory in a memory system employing a directory-based cache coherency scheme, the method comprising:

providing a memory unit comprising a plurality of memory modules each storing a plurality of cache lines, with each cache line comprising a plurality of data bits and a plurality of informational bits;

providing a common data bus coupled to all of the memory modules and configured to read/write data bits from/to all of the memory modules;

providing a plurality of information buses, each information bus coupled to a corresponding one of the memory modules and configured to read/write informational bits of cache lines from/to its corresponding memory module; and

reading from a first memory module a plurality of data bits and a plurality of informational bits of a first cache line via the common data bus and the information bus corresponding to the first memory module, and simultaneously writing a plurality of informational bits of a second cache line to a second memory module via the information bus corresponding to the second memory module.

18. The method of claim 17 , further comprising:

providing a memory unit comprising a plurality of dual in-line memory modules (DIMMs).

19. The method of claim 18 , further comprising:

providing DIMMs comprising a plurality of random access memory (RAM) devices.

20. The method of claim 19 , further comprising:

partitioning the plurality of RAM devices to form a sub-plurality of RAM devices for storing data bits, a sub-plurality of RAM devices for storing ECC bits, and a sub-plurality of RAM devices for storing directory tag bits.

21. The method of claim 17 , further comprising:

providing an address/control bus coupled to each memory module.

22. The method of claim 17 , further comprising:

providing as part of the address/control bus a plurality of ECC/tag control lines, one coupled to each memory module, wherein each ECC/tag control line is configured to enable/disable the ability of ECC and directory tag bits to be written to its corresponding memory module.

23. A method of controlling memory access in a memory system employing a directory-based cache coherency scheme, the method comprising:

reading from a first memory module of a memory unit a plurality of data bits of a first cache line via a memory bus and a plurality of informational bits of the first cache line via a first information bus coupled only to the first memory module, and simultaneously writing to a second memory module of the memory unit a plurality of informational bits of a second cache line via a second information bus coupled only to the second memory module, wherein the data bus coupled to and shared by the first and second memory modules.