LCD array substrate and fabrication method thereof
View Patent ↗An LCD array substrate includes a plurality of gate lines arranged in a first direction; a plurality of data lines arranged in a second direction to cross the plurality of gate lines; a semiconductor layer formed at overlapping regions of the gate lines and the data lines and extending a predetermined length from the overlapping regions over the gate lines; a drain electrode spaced apart from the overlapping regions of the gate and data lines and disposed partially in contact with the semiconductor layer, the drain electrode having ends extended beyond the semiconductor layer and the gate line; and a pair of pixel electrodes disposed on opposing sides of the gate line and electrically connected with the drain electrode.
1. An LCD array substrate, comprising:
a plurality of gate lines arranged in a first direction;
a plurality of data lines arranged in a second direction to cross the plurality of gate lines;
a semiconductor layer formed at overlapping regions of the gate lines and the data lines and extending a predetermined length from the overlapping regions over the gate lines;
a drain electrode spaced apart from the overlapping regions of the gate and data lines and disposed partially in contact with the semiconductor layer, the drain electrode having ends extended beyond the semiconductor layer and a respective gate line of the plurality of gate lines; and
a pair of pixel electrodes disposed on opposing sides of the gate line and electrically connected with the drain electrode.
2. The LCD array substrate according to claim 1 , wherein the pair of pixel electrodes are connected to the ends of the drain electrode.
3. The LCD array substrate according to claim 1 , wherein each one of the pixel electrodes is formed within a pixel region defined by a pair of adjacent data lines and regions adjacent to one of the gate lines crossing the pair of data lines.
4. The LCD array substrate according to claim 1 , wherein the pair of pixel electrodes are respectively formed to be spaced apart by predetermined intervals from the gate line passing through a pixel region, and the pair of pixel electrodes defining a unit pixel with respect to the pixel region.
5. The LCD array substrate according to claim 1 , wherein a portion of the semiconductor layer between the data line and the drain electrode defines a channel allowing a signal to be transferred from the data line to the drain electrode according to a signal from the gate line.
6. The LCD array substrate according to claim 1 , wherein the plurality of data lines and the plurality of gate lines cross at substantially right angles.
7. The LCD array substrate according to claim 1 , wherein the gate lines and the data lines at the overlapping regions of the gate and data lines directly form gate electrodes and source electrodes for a thin film transistor.
8. The LCD array substrate according to claim 1 , wherein the drain electrode spans entire widths of the semiconductor layer and the respective gate line.