Semiconductor capacitive element, method for manufacturing same and semiconductor device provided with same
View Patent ↗A semiconductor capacitor configured so as to use buried wirings, as electrodes, formed in an interlayer dielectric is provided on a semiconductor substrate which is capable of preventing an increase in a number of manufacturing processes with occurrence of parasitic capacity being suppressed. The semiconductor capacitor has a capacitive insulating film made up of an etching stopper film formed only in a region being sandwiched between a via plug serving as an upper electrode and a lower electrode, in which the capacitive insulating film is not formed in a region other than the facing region.
1. A semiconductor capacitive element using wirings buried in an interlayer dielectric on a semiconductor substrate as electrodes comprising:
a lower electrode being buried in a first interlayer dielectric formed on said semiconductor substrate;
an upper electrode being buried in a second interlayer dielectric formed via an etching stopper film on said first interlayer dielectric; and
a capacitive insulating film made up of said etching stopper film being formed only in a region being sandwiched between said upper electrode and said lower electrode.
2. The semiconductor capacitive element according to claim 1 , wherein a thickness of said capacitive insulating film is smaller than that of said etching stopper film in said region being sandwiched between said first interlayer dielectric and said second interlayer dielectric.
3. The semiconductor capacitive element according to claim 1 , wherein a dielectric constant of said etching stopper film is larger than that of said second interlayer dielectric.
4. The semiconductor capacitive element according to claim 1 , wherein a third interlayer dielectric is formed on said second interlayer dielectric and said upper electrode is connected to wirings buried in said third interlayer dielectric.
5. A semiconductor device provided with a semiconductor capacitive element using wirings buried in an interlayer dielectric on a semiconductor substrate as electrodes, said semiconductor capacitive element comprising:
a lower electrode being buried in a first interlayer dielectric formed on said semiconductor substrate;
an upper electrode being buried in a second interlayer dielectric formed via an etching stopper film on said first interlayer dielectric; and
a capacitive insulating film made up of said etching stopper film being formed only in a region being sandwiched between said upper electrode and said lower electrode.
6. The semiconductor device according to claim 5 , wherein a thickness of said capacitive insulating film is smaller than that of said etching stopper film in said region being sandwiched between said first interlayer dielectric and said second interlayer dielectric.
7. The semiconductor device according to claim 5 , wherein a dielectric constant of said etching stopper film is larger than that of said second interlayer dielectric.
8. The semiconductor device according to claim 5 , wherein a third interlayer dielectric is formed on said second interlayer dielectric and said upper electrode is connected to wirings buried in said third interlayer dielectric.