Vertical MOSFET reduced in cell size and method of producing the same
View Patent ↗In a vertical MOSFET comprises: a semiconductor layer ( 1, 2, 9, 10 ) having first and second surfaces opposite to each other and trenches ( 6 ) formed on the first surface; trench gates ( 8 ) formed in the trenches; a unit cell formed in a region of the semiconductor layer surrounded by the trench gates, the unit cell comprising a base layer ( 9 ) and a source layer ( 10 ) formed on the base layer and having the first surface as a principal semiconductor surface, the unit cell having a contact hole ( 12 ) formed on a center of the principal semiconductor surface and extending from the principal semiconductor surface through the source layer to an inside of the base layer; a contact ( 17 ) formed in the contact hole; a source electrode ( 18 ) formed on the contact; and a drain electrode ( 19 ) formed on the second surface, the contact is formed to a depth different to a peak depth which is a position having a maximum impurity-concentration in a depth direction of the base layer. The unit call further comprises a base contact layer ( 14 ) formed within the base layer so as to enclose a bottom of the contact and to bring the base contact layer into contact with the bottom of the contact.
1. A vertical MOSFET comprising: a semiconductor layer ( 1 , 2 , 9 , 10 ) having first and second surfaces opposite to each other and a pair of trenches ( 6 ) formed on said first surface; a pair of trench gates ( 8 ) formed in said pair of trenches; a unit cell formed in a region of said semiconductor layer surrounded by said pair of trench gates, said unit cell comprising a base layer ( 9 ) and a source layer ( 10 ) formed on said base layer and having said first surface as a principal semiconductor surface, said unit cell having a contact hole ( 12 ) formed on a center of said principal semiconductor surface and extending from said principal semiconductor surface through said source layer to an inside of said base layer; a contact ( 17 ) formed in said contact hole; a source electrode ( 18 ) formed on said contact; and a drain electrode ( 19 ) formed on said second surface; wherein said contact is formed to a depth different to a peak depth which is a position having a maximum impurity-concentration in a depth direction of said base layer, said unit cell further comprising a base contact layer ( 14 ) formed within said base layer so as to enclose a bottom of said contact and to bring said base contact layer into contact with the bottom of said contact.
2. A vertical MOSFET as claimed in claim 1 , wherein d and z have a relationship given by d<z−0.1 μm or d>z+0.1 μm, where d represents the depth of said contact from said principal semiconductor surface and where z represents the peak depth from said principal semiconductor surface.
3. A vertical MOSFET as claimed in claim 1 , wherein said base contact layer is formed within said base layer so as to enclose only the bottom of said contact and to bring said base contact layer into contact with only the bottom of said contact.
4. A vertical MOSFET as claimed in claim 1 , wherein said contact hole is with a metal which serves as said contact and has a flattened surface, said source electrode being formed on the flattened surface of said metal and having another flattened surface.
5. A vertical MOSFET as claimed in claim 1 , wherein said unit cell further comprising a metal silicide ( 15 ) formed between the bottom of said contact and said base contact layer, between a side wall of said contact and said source layer, and between the side wall of said contact and said base layer.
6. A vertical MOSFET as claimed in claim 1 , wherein said contact hole has a tapered shape gradually decreased in aperture size from said first surface towards said second surface.