Apparatus and method for adjusting instruction thread priority in a multi-thread processor
View Patent ↗Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
1. A method for controlling the cycle-by-cycle interleaving of instructions between a number of instruction threads in a simultaneous multithreading processor, each respective instruction thread being stored in a respective queue of the simultaneous multithreading processor and being made up of instructions that have previously been fetched by a fetcher unit of the processor for execution, the method including the steps of:
(a) receiving a first priority signal indicating a first base input processing priority associated with a first instruction thread included in the number of instruction threads;
(b) receiving a feedback signal associated with one of the instruction threads;
(c) adjusting the first base input processing priority to generate a first adjusted input processing priority in response to the feedback signal;
(d) applying an interleave rule to the first adjusted input processing priority and at least one other thread processing priority to generate a thread selection control signal for controlling the interleaving of instructions from the number of instruction threads, the interleave rule specifying a relative frequency at which instructions are to be taken from each of the number of instruction threads; and
(e) applying the thread selection control signal to control a selection multiplexer having a respective input for each one of the number of instruction threads.
2. The method of claim 1 further including the step of selecting between the first base input processing priority and the first adjusted input processing priority in response to the feedback signal.
3. The method of claim 1 wherein the step of receiving the feedback signal includes receiving a signal associated with a long-latency event.
4. The method of claim 3 wherein the long-latency event is associated with the first instruction thread and the step of adjusting the first base input processing priority includes decreasing the first base input processing priority.
5. The method of claim 3 wherein the long-latency event is associated with an instruction thread other than the first instruction thread and the step of adjusting the first base input processing priority includes increasing the first base input processing priority.
6. The method of claim 1 further including the steps of:
(a) receiving a second priority signal indicating a second base input processing priority associated with a second instruction thread included in the number of instruction threads;
(b) adjusting the second base input processing priority to generate a second adjusted input processing priority in response to the feedback signal; and
(c) applying the interleave rule to the first adjusted input processing priority and at least the second adjusted input processing priority to generate the thread selection control signal for controlling the interleaving of instructions from the number of instruction threads.