Dual-gate CMOS semiconductor device and dual-gate CMOS semiconductor device manufacturing method
View Patent ↗A manufacturing method for a dual-gate CMOS semiconductor device that suppresses mutual diffusion of P type impurities and N type impurities in a gate electrode. An NMOS part and a PMOS part are formed on a semiconductor substrate. A polycrystalline silicon layer is formed on the NMOS part and the PMOS part, and consists of an N type impurity containing polycrystalline silicon layer and a P type impurity containing polycrystalline silicon layer. A first conductive layer is formed on the polycrystalline silicon layer so as to include a groove region, in which the first conductive layer is not formed, on a predetermined region including a boundary between the N type impurity containing polycrystalline silicon layer and the P type impurity containing polycrystalline silicon layer.
1. A dual-gate CMOS semiconductor device comprising:
a semiconductor substrate having an NMOS region and a PMOS region;
a first polycrystalline silicon layer formed on the NMOS region of the semiconductor substrate, the first polycrystalline silicon layer having N type impurities;
a second polycrystalline silicon layer formed on the PMOS region of the semiconductor substrate, the second polycrystalline silicon layer having P type impurities; and
a first conductive layer formed on the first and second polycrystalline silicon layers, the first conductive layer having an opening between the first and second polycrystalline silicon layers,
wherein the first and second polycrystalline silicon layers and the first conductive layer are a gate electrode, and
wherein the first conductive layer is a tungsten silicide layer and an insulating layer almost equal in height to the first conductive layer is formed in the opening.
2. A dual-gate CMOS semiconductor device according to claim 1 , wherein a sidewall made of a nitride film is formed at least on a side surface of the gate electrode.
3. A dual-gate CMOS semiconductor device comprising:
a semiconductor substrate having an NMOS region and a PMOS region;
a first polycrystalline silicon layer formed on the NMOS region of the semiconductor substrate, the first polycrystalline silicon layer having N type impurities;
a second polycrystalline silicon layer formed on the PMOS region of the semiconductor substrate, the second polycrystalline silicon layer having P type impurities;
a first conductive layer formed on the first and second polycrystalline silicon layers, the first conductive layer having an opening between the first and second polycrystalline silicon layers; and
an insulating material formed in the opening directly on the first and second polycrystalline silicon layers,
the first and second polycrystalline silicon layers and the first conductive layer are a gate electrode.
4. A dual-gate CMOS semiconductor device according to claim 3 , wherein a second conductive layer having a predetermined thickness is formed in the first and second polycrystalline silicon layers at a bottom of the opening.
5. A dual-gate CMOS semiconductor device according to claim 4 , wherein the second conductive layer is a cobalt silicide layer.
6. A dual-gate CMOS semiconductor device according to claim 3 , wherein a sidewall made of a nitride film is formed at least on a side surface of the gate electrode.
7. A dual-gate CMOS semiconductor device according to claim 3 , wherein the first conductive layer is tungsten silicide layer.