Methods and apparatus for providing cache state information
View Patent ↗According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for improving the accuracy of information available to a cache coherence controller are provided in order to allow the cache coherence controller to reduce the number of transactions in a multiple cluster system. Cache state information is provided to a home cluster cache coherence controller to allow silent evictions of shared memory lines and change to dirty associated intervening requests to be efficiently handled.
1. A computer system, comprising:
a home cluster including a first plurality of nodes and a home cache coherence controller associated with a coherence directory, the coherence directory having state information corresponding to home cluster memory lines cached remotely;
a request cluster including a second plurality of nodes and a request cache coherence controller, the request cache coherence controller configured to probe request cluster nodes to obtain cache state information associated with a memory line, wherein the cache state information is provided to a request cluster processor and to the home cache coherence controller to provide the home cache coherence controller with accurate cache state information for updating the coherence directory.
2. The computer system of claim 1 , wherein the probe is associated with a read request.
3. The computer system of claim 2 , wherein the cache state information provided to the request cluster processor indicates that the memory line is held in the shared state in the request cluster.
4. The computer system of claim 3 , wherein the coherence directory indicates that the memory line is shared by the request cluster.
5. The computer system of claim 4 , wherein the cache state information provided to the home cache coherence controller indicates that the memory line is held in the shared state in the request cluster.
6. The computer system of claim 5 , wherein the coherence directory is maintained to indicate that the request cluster has a shared copy of the memory line after the cache state information is provided.
7. The computer system of claim 1 , wherein the cache state information provided to the request cluster processor indicates that the memory line is held in the exclusive state in the request cluster.
8. The computer system of claim 7 , wherein the coherence directory indicates that the memory line is shared by the request cluster.
9. The computer system of claim 8 , wherein the cache state information provided to the home cache coherence controller indicates that the memory line is held in the exclusive state in the request cluster.
10. The computer system of claim 9 , wherein the coherence directory is updated to indicate that the request cluster has ownership of the memory line in a modified state after the cache state information is provided if no other clusters are identified as having a shared copy of the memory line.
11. The computer system of claim 1 , wherein the cache state information provided to the home cluster indicates that the memory line is held in a shared or exclusive state.
12. A method, comprising:
receiving a read request associated with a memory line from a first processor in a first cluster;
probing nodes in the first cluster to obtain cache state information associated with the memory line;
forwarding cache state information to the first processor;
forwarding cache state information to a second cluster to update a coherence directory in the second cluster, wherein the coherence directory provides state information of cache memory lines.
13. The method of claim 12 , wherein the first cluster is a request cluster and the second cluster is a home cluster.
14. The method of claim 13 , wherein the cache state information provided to the request cluster processor indicates that the memory line is held in the shared state in the request cluster.
15. The method of claim 14 , wherein the coherence directory indicates that the memory line is shared by the request cluster.
16. The method of claim 15 , wherein the cache state information provided to the home cache coherence controller indicates that the memory line is held in the shared state in the request cluster.
17. The method of claim 16 , wherein the coherence directory is maintained to indicate that the request cluster has a shared copy of the memory line after the cache state information is provided.
18. The method of claim 13 , wherein the cache state information provided to the request cluster processor indicates that the memory line is held in the exclusive state in the request cluster.
19. The method of claim 18 , wherein the coherence directory indicates that the memory line is shared by the request cluster.
20. The method of claim 19 , wherein the cache state information provided to the home cache coherence controller indicates that the memory line is held in the exclusive state in the request cluster.
21. The method of claim 20 , wherein the coherence directory is updated to indicate that the request cluster has ownership of the memory line in a modified state after the cache state information is provided if no other clusters are identified as having a shared copy of the memory line.
22. An apparatus, comprising:
means for receiving a read request associated with a memory line from a first processor in a first cluster;
means for probing nodes in the first cluster to obtain cache state information associated with the memory line;
means for forwarding cache state information to the first processor;
means for forwarding cache state information to a second cluster to update a coherence directory in the second cluster, wherein the coherence directory provides state information of cache memory lines.
23. A computer system, comprising:
a home cluster including a first plurality of nodes and a home cache coherence controller associated with a coherence directory, the coherence directory having state information corresponding to home cluster memory lines cached remotely;
a request cluster including a second plurality of nodes and a request cache coherence controller, the request cache coherence controller configured to forward a change to dirty request to a home cluster and probe request cluster nodes to obtain cache state information associated with a memory line, wherein the cache state information is provided to a request cluster processor and to the home cache coherence controller to provide the home cache coherence controller with information to determine whether the change to dirty request was successful.
24. The computer system of claim 23 , wherein the coherence directory indicates that the memory line is shared or owned by the request cluster when the change to dirty request causes a serialization point to lock the memory line.
25. The computer system of claim 24 , wherein the cache state information provided to the request cluster indicates that the memory line is held in a modified state in the request cluster.
26. The computer system of claim 25 , wherein the coherence directory is updated to indicate that the request cluster has a modified copy of the memory line after the cache state information is provided, indicating that the change to dirty request was successful.
27. The computer system of claim 23 , wherein an intervening request for the memory line from a remote cluster is received after a request cluster processor issues the request but before the request causes a serialization point to lock the memory line.
28. The computer system of claim 27 , wherein the coherence directory indicates that the memory line is owned by a remote cluster and the memory line is in an owned or modified state.
29. The computer system of claim 28 , wherein the owned or modified state indicates that the memory line was invalidated by the intervening request.
30. The computer system of claim 29 , wherein the change to dirty request invalidates all copies of the memory line in all non-request clusters and acquires data from the remote cluster owning the memory line.
31. The computer system of claim 23 , wherein an intervening request for the memory line from a remote cluster is received after a request cluster processor issues the request but before the request causes a serialization point to lock the memory line.
32. The computer system of claim 31 , wherein the coherence directory indicates that the memory line is held in an invalid or shared state, the request cluster not having a shared copy of the memory line.
33. The computer system of claim 32 , wherein the invalid or shared state indicates that the memory line was invalidated by the intervening request and the memory line is not owned by any particular cluster.
34. The computer system of claim 33 , wherein the change to dirty request invalidates all copies of the memory line in all non-request clusters but fails because no data is supplied to the request cluster.
35. The computer system of claim 23 , wherein the change to dirty request is a request to change a request cluster shared memory line to a modified state.
36. The computer system of claim 23 , wherein the change to dirty request is a request to change a request cluster owned memory line to a modified state.
37. The computer system of claim 23 , wherein the cache state information provided to the home cluster indicates that the memory line is held in a modified or invalid state.