Parameter generation for interleavers
View Patent ↗An interleaver parameter generator circuit used to calculate and generate on an as needed basis interleaver parameters for interleaving blocks of information of varying lengths in accordance with a pseudorandom pattern defined by the 3GPP standard. The interleaver parameter generator circuit calculates and generates the defined interleaver parameters based on an input parameter that represents the length of the block of information to be interleaved. At least one of the defined parameters is calculated and generated using a decomposed form of its definition. The interleaver parameter generator circuit uses well known circuit blocks such as multipliers, subtractors, Compare-and-Select circuits and other circuits to calculate and generate the defined parameters.
1. An interleaver parameter generator comprising:
a processing circuit having at least one input to receive a corresponding input parameter and a plurality of outputs to provide a corresponding plurality of interleaver parameters to an interleaver during generation of interleaving patterns, wherein the processing circuit is configured to calculate said interleaver parameters based at least in part on a first input parameter, where at least one of the interleaver parameters is calculated during generation of the interleaving patterns using a decomposed form that implements modulus (MOD) operations without division.
2. The interleaver parameter generator of claim 1 further comprising a first storage circuit in which the at least one interleaver parameter calculated using the decomposed form is stored where the first storage circuit is coupled to the processing circuit.
3. The interleaver parameter generator of claim 1 where the processing circuit comprises at least one logic circuit used to calculate at least one interleaver parameter.
4. The interleaver parameter generator of claim 1 where the processing circuit is an ASIC.
5. The interleaver parameter generator of claim 1 where the processing circuit is constructed with FPGA circuitry.
6. The interleaver parameter generator of claim 1 where the interleaver parameters include at least one of R, C, p, v, PRUNVAL and S(i) and said interleaver parameters are calculated using logic circuits as part of the processing circuit, where the at least one interleaver parameter calculated using the decomposed form defines S(i).
7. The interleaver parameter generator of claim 6 where a first logic circuit calculates S(i) and comprises:
a counter circuit that provides values for n=1, . . . , v−1;
a first multiplier used to calculate v·S(i−1);
a second multiplier used to calculate p·n for n=0, 1, . . . , v−1;
a compare circuit coupled to the first multiplier and the second multiplier so as to generate an enable signal indicating p·n is greater than v·S(i−1);
a memory circuit coupled to the second multiplier to store p·n values for at least n and n−1; and
a subtractor circuit coupled to the first multiplier and the memory circuit so as to calculate v·S(i−1)−p·(n−1) for S(i).
8. The interleaver parameter generator of claim 6 where a first logic circuit calculates S(i) and comprises:
a pn generator circuit that generates p·n values for n=1, . . . , v−1;
a multiplier circuit to calculate v·S(i−1);
a compare and select circuit, coupled to the pn generator circuit and multiplier circuit, which compares the p·n values to v·S(i−1) and selects the largest p·n value that is not greater than v·S(i−1); and
a subtractor circuit coupled to the multiplier circuit and to the compare and select circuit to calculate S(i)=v·S(i−1)−p·n for said largest p·n value.
9. The interleaver parameter generator of claim 6 where a first logic circuit calculates S(i) and comprises:
a multiplier that calculates v·S(i−1);
a processor, coupled to the multiplier, to generate p·n values for n=1, . . , v−1, select the greatest p·n value that is not greater than v·S(i−1), and subtract said greatest p·n value from v·S(i−1) thus calculating S(i).
10. The interleaver parameter generator of claim 1 , further comprising:
a first storage circuit containing possible values for first and second interleaver parameters and from which said first and second interleaver parameters are calculated, where the first storage circuit is coupled to the processing circuit.
11. The interleaver parameter generator of claim 1 , the processing circuit configured to receive an input parameter K indicative of a block length for information to be stored in a matrix having R rows and C columns and generate S(i) sequence parameter values for i=0, 1, ., ., ., p−2, where p is a smallest possible prime number that satisfies the condition
p
+
1
≥
K
R
,
based at least in part on a decomposed form that implements modulus (MOD) operations without division, the interleaver parameter generator further comprising:
a storage circuit, in communication with the processing circuit, to store said S(i) sequence parameter values for use by an interleaver during generation of interleaving patterns.
12. The interleaver parameter generator of claim 11 wherein the processing circuit generates the S(i) sequence parameter values during generation of the interleaving patterns.
13. The interleaver parameter generator of claim 11 , the processing circuit including:
a logic circuit to receive the input parameter K and generate interleaver parameter values for R rows of the matrix based at least in part on said input parameter K.
14. The interleaver parameter generator of claim 11 , the processing circuit including:
a logic circuit to receive the input parameter K and generate interleaver parameter values for the smallest possible prime number (p) that satisfies the condition
p
+
1
≥
K
R
and a primitive root (v) of said prime number based at least in part on said input parameter K and interleaver parameter values for R rows of the matrix.
15. The interleaver parameter generator of claim 11 , the processing circuit including:
a logic circuit to receive the input parameter K and generate interleaver parameter values for C columns of the matrix based at least in part on said input parameter K and interleaver parameter values for R rows of the matrix, the smallest possible prime number (p) that satisfies the condition
p
+
1
≥
K
R
,
and a primitive root (v) of said prime number.
16. The interleaver parameter generator of claim 11 , the processing circuit including:
a logic circuit to receive the input parameter K and generate interleaver parameter values for a number of locations that can be pruned from the matrix (PRUNVAL) based at least in part on said input parameter K and interleaver parameter values for R rows of the matrix, and C columns of the matrix.
17. A method for generating an interleaver parameter using the interleaver parameter generator of claim 1 , comprising:
a) receiving an input parameter K indicative of a block length for information to be stored in a matrix having R rows and C columns;
b) generating S(i) sequence parameter values for i=0, 1, ., ., ., p−2, where p is a smallest possible prime number that satisfies the condition
p
+
1
≥
K
R
,
based at least in part on a decomposed form that implements modulus (MOD) operations without division; and
c) storing said S(i) sequence parameter values for use by an interleaver during generation of interleaving patterns.
18. The method of claim 17 wherein the generating in b) is during generation of the interleaving patterns by the interleaver.
19. The method of claim 17 , further including:
d) receiving the input parameter K; and
e) generating interleaver parameter values for R rows of the matrix based at least in part on said input parameter K.
20. The method of claim 17 , further including:
d) receiving the input parameter K; and
e) generating interleaver parameter values for the smallest possible prime number (p) that satisfies the condition
p
+
1
≥
K
R
and a primitive root (v) of said prime number based at least in part on said input parameter K and interleaver parameter values for R rows of the matrix.