Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor

1. A method for synchronizing multiple threads in an out of order microprocessor, comprising the steps of:

identifying a synchronizing instruction in a sequence of instructions for a first thread executing on the microprocessor;

in response to identifying the synchronizing instruction, halting execution of instructions in all other remaining threads that are executing on the microprocessor;

executing the synchronizing instruction in said first thread;

resuming execution of instructions in the remaining threads after executing the synchronizing instruction;

marking a non-executed instruction that is slated for execution in each halted remaining thread with a trap;

wherein instructions slated for execution prior to the instruction marked with a trap in each of the other remaining threads are retired before the synchronizing instruction is executed;

wherein said synchronizing instruction is at least one that reads a system array directly, switches memory translation context, and employs a branch prediction scheme; and

wherein the marking of a non-executed instruction with a trap in at least one of the other threads comprises adding an extra data bit to the non-executed instruction that identifies the trap as a hardware trap.

2. The method of claim 1 wherein said synchronizing instruction is one that employs a branch prediction scheme.

3. The method of claim 1 wherein said synchronizing instruction is one that switches memory translation context.

4. An out of order microprocessor for synchronizing threads, comprising:

a detection facility for detecting events in the first thread requiring microprocessor synchronization; and

a trap facility for inserting a trap in the second thread upon detection of an event in the first thread that requires microprocessor synchronization, wherein said trap is inserted in a next non-executed instruction slated for execution in the second thread, and wherein all instructions slated for execution prior to the instruction marked with a trap in the second thread retire before executing the synchronizing instruction in the first thread;

marking a non-executed instruction that is slated for execution in each halted remaining thread with a trap;

wherein the marking of a non-executed instruction with a trap in at least one of the other threads comprises adding an extra data bit to the non-executed instruction that identifies the trap as a hardware trap:

wherein said trap is used as a sequential marker within the instruction pipeline of the second thread: and

wherein said trap is used in at least one of monitoring individual instructions in an instruction pipeline, debugging an executing instruction set and evaluating performance of executing threads on a microprocessor.

5. The microprocessor of claim 4 , wherein, after execution of the synchronizing instruction in a first thread, all instructions slated for execution after the trapped instruction in the second thread are flushed and refetched.

6. In a microprocessor running multiple threads simultaneously, a method for inserting a trap into a next instruction slated for execution in one of said running threads, comprising the steps of:

identifying a last executed instruction in said one running thread on said microprocessor;

marking the next instruction slated for execution within said one running thread with a trap prior to the execution of said next instruction by adding a data bit to the next non-executed instruction slated for execution within said running thread;

wherein said trap triggers a state machine capable of signaling the microprocessor upon the execution of the instruction marked with said trap:

wherein said trap is used as a sequential marker for synchronization of multiple threads in an out of order microprocessor:

wherein said trap may be in at least one of monitoring individual instructions in an instruction pipeline and debugging an executing instruction set; and

said trap is inserted into a running thread on a microprocessor capable of executing multiple threads concurrently following the identification of an instruction requiring microprocessor synchronization in a second thread running on said microprocessor.

7. The method of claim 6 , wherein said trap may be utilized in evaluating the microprocessor efficiency in instruction execution.