Method and auxiliary device for testing a RAM memory circuit
View Patent ↗The testing of a RAM memory circuit containing a multiplicity of memory cells can in each case be selected in groups of n≧1 memory cells by using an applied address information item in order to write in or read out groups of in each case n data. According to the invention, in a test write cycle, a plurality i=j*m of the memory cell groups are selected, where j and m are in each case integers ≧2, and the same datum is written into all the memory cells of in each case m selected memory cell groups. In a subsequent read cycle, the i memory cell groups selected in the write cycle are selected and read in a sequence such that the read-out data groups from in each case m memory cell groups at which the same datum was written in are provided simultaneously or in direct succession as a read data block comprising m*n data. Each time a read data block is provided, a compressed test result is determined and provided; the result indicates if all m*n data of the read data block provided correspond to the datum written therein.
1. A test auxiliary device for testing a RAM memory circuit containing a multiplicity of memory cells, an input/output device for receiving and outputting memory data, having an address input for applying address information items, and having a selection device for selecting groups of n ≧1 memory cells depending on the address information being applied and for one of writing in and reading out a group of n data at the respectively selected memory cell group, the test auxiliary device comprising:
a test control device for applying control, data, and address information items to the selection device;
in a test write operation, said test control device applying subsequentially test data for j subsequent write cycles at a first clock speed;
in each write cycle, the selection device selecting m memory cell groups, where j and m are in each case integers ≧2, and writing subsequentially, on a group by group basis, one of said test data as an identical datum to all of the memory cells of the m selected memory cell groups at a second clock speed faster than said first clock speed;
in a test read operation, said test control device carrying out j subsequent read cycles at a third clock speed;
in each read cycle, the selection device reading data subsequentially, on a group by group basis, from the m selected memory cell groups as a read data block including m*n data at a fourth clock speed faster than said third clock speed;
an evaluation device determining and providing a compressed test result indicating if all of the m*n data of the read data block correspond to the identical datum written therein; and
said evaluation device outputting subsequentially said compressed test result.
2. The test auxiliary device according to claim 1 , wherein the RAM memory circuit further has a clock generator for generating a clock signal, operates normally with a data rate equal to a rate of the clock signal, and the input/output device thereof is to be connected to the selection device via an n-bit data bus having lines; the test auxiliary device further comprising:
an address changeover unit generating, from each of the address information items, a sequence of m different addresses for selecting m different memory cell groups with the rate of the clock signal;
a switch connecting all of the lines of the data bus to a test data terminal for applying a test data bit in the write cycle and to the evaluation device in the read cycle; and
a comparator in the evaluation device for, in the read cycle, comparing each bit of n-bit data words appearing in m directly successive periods of the clock signal on the data bus with the same test data bit and for providing a result after comparing as a compressed test result.
3. The test auxiliary device according to claim 1 , wherein the RAM memory circuit normally operates with a data rate equal to m times a rate of a clock signal and has m parallel n-bit branch buses leading to the selection device and is to be connected cyclically to the input/output device via a multiplexer, the multiplexer being switchable at the data rate, the selection device being controllable at the rate of the clock signal in order. simultaneously to select from m disjoint areas of the memory bank, at least one of the memory cell groups existing for each of the m branch buses; the test auxiliary device further comprising:
a comparator having a m*n-bit signal input, having a reference input for receiving a test data bit, and an output for indicating as a compressed test result if all the bits of the m*n-bit signal input correspond to the test data bit; and
a switch connecting all the lines of the m branch buses to a test data terminal for applying the test data bit in the write cycle and to the n*m-bit signal input of the comparator of the evaluation device in the read cycle.
4. The test auxiliary device according to claim 1 , wherein m is equal to 2*, where x is an integer at most equaling 1.
5. The test auxiliary device according to claim 1 for testing the RAN memory circuit normally operating with a data rate equal to p times a rate of a clock signal, and having p parallel n-bit branch buses leading to the selection device, and connected cyclically to the input/output device via a multiplexer, the multiplexer being switchable at the data rate, the selection device being controllable at the rate of the clock signal in order simultaneously to select from p disjoint areas of the memory bank, in each case a memory cell group existing for each or the p branch buses; the test auxiliary device further comprising:
an address changeover unit generating from each of the address information items a sequence of r different addresses with the rate of the clock signal for selecting r different memory cell groups in each of the p areas of the memory bank;
a comparator having a p*n-bit signal input, having a reference input for receiving a test data bit, and an output indicating a partial result “test passed” precisely when all bits of the p*n-bit signal input correspond to the test data bit;
a switch connecting all of the lines of all of the p branch buses to a test data terminal for applying the test data bit in the write cycle and to the p*n-bit signal input of the comparator of the evaluation device in the read cycle; and
a device indicating as a compressed test result if all r partial results having been supplied in r directly successive periods of the clock signal indicate “test passed”.
6. The test auxiliary device according to claim 1 , wherein the test auxiliary device is integrated with the memory circuit on a single semiconductor chip.