IP Library Granted Patent US 6,900,551
Granted Patent B2
US 6,900,551 · App. 10/430,279 · Granted May 31, 2005

Semiconductor device with alternate bonding wire arrangement

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Quick Facts
Patent No.
US 6,900,551
App. No.
10/430,279
Granted
May 31, 2005
Kind
B2
Abstract

A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.

Claims (21)

1. A semiconductor device comprising:

a semiconductor chip;

a wiring substrate having the semiconductor chip mounted on a main surface;

a plurality of electrode pads, each having a first connection end and a second connection end, arranged on a main surface of the semiconductor chip along at least one side of the semiconductor chip, the first connection ends being closer to the side of the semiconductor chip than the second connection ends;

a plurality of connecting portions arranged in a first row and a second row on the main surface of the wiring substrate between the side of the semiconductor chip and an outer edge of the wiring substrate, the first row being closer to the side of the semiconductor chip than the second row;

a plurality of wires, connected to the plurality of electrode pads and the plurality of connecting portions, to connect each of the first row connecting portions to the first connection end of a corresponding electrode pad, and to connect each of the second row connecting portions to the second connection end of a corresponding electrode pad; and

a resin sealing body sealing up the semiconductor chip and the plurality of wires.

2. The semiconductor device according to claim 1 , wherein each of the plurality of electrode pads has a rectangular form including two long opposite sides extending in a direction away from the side of the semiconductor chip.

3. The semiconductor device according to claim 1 , wherein the plurality of electrode pads are arranged in a single row.

4. The semiconductor device according to claim 3 , wherein the plurality of electrode pads are alternatingly connected to the first and second rows of the connecting portions.

5. The semiconductor device according to claim 4 , wherein the first and second rows of the connecting portions are arranged in a zigzag manner.

6. The semiconductor device according to claim 1 , wherein the plurality of connecting portions are arranged in a zigzag manner by placing the first row of connecting portions and the second row of connecting portions alternatingly.

7. The semiconductor device according to claim 1 , wherein the pitch of the plurality of electrode pads is narrower than the pitch of the plurality of connecting portions.

8. The semiconductor device according to claim 1 , wherein the wires connecting the first row of connecting portions to the plurality of electrode pads are shorter than the wires connecting the second row of connecting portions to the plurality of electrode pads.

9. The semiconductor device according to claim 1 , wherein the plurality of wires are connected to the plurality of electrode pads and the plurality of connecting portions using nail head bonding.

10. The semiconductor device according to claim 1 , wherein the resin sealing body is formed by transfer molding.

11. The semiconductor device according to claim 1 , wherein each of the plurality of electrode pads includes:

a rectangular form having two long opposite sides extending in a direction away from the side of the semiconductor chip, and

a bonding surface having a probe needle contact mark formed between the first and second connection ends of the electrode pad.

12. The semiconductor device according to claim 11 , wherein the long sides of each of the plurality of electrode pads are longer than a first connection end length and a second connection end length combined.

13. The device according to claim 1 , wherein a loop height of the wires attached to the first row of connecting portions is smaller than a loop height of the wires attached to the second row of connecting portions.

Assignments (6)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2014
From: HITACHI ULSI SYSTEMS CO., LTD.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 032859/0252 →
CHANGE OF NAME Recorded Aug 13, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024864/0635 →
MERGER Recorded Aug 13, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024879/0190 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2003
From: HITACHI, LTD.
To: RENESAS TECHNOLOGY CORPORATION
Reel/Frame 014190/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2003
From: MATSUZAWA, TOMOO; NISHITA, TAKAFUMI; NAKAJIMA, YASUYUKI; MORITA, TOSHIAKI
To: HITACHI, LTD.; HITACHI ULSI SYSTEMS CO., LTD.
Reel/Frame 014045/0736 →