Multilayer circuit board
View Patent ↗A technique for eliminating electrically conductive vias is disclosed. In one embodiment, the technique is realized as an improved multilayer circuit board for eliminating electrically conductive vias. The multilayer circuit board has a top layer and a buried layer separated by at least one dielectric layer, wherein the buried layer includes an electrically conductive power plane portion and an electrically conductive ground plane portion. The improvement comprises a cavity in the multilayer circuit board extending through the top layer and the at least one dielectric layer so as to expose at least a portion of the power plane portion and the ground plane portion of the buried layer within the cavity. The cavity is sized to accommodate an electronic component therein such that the electronic component makes electrical contact with the exposed portion of the power plane portion and the ground plane portion of the buried layer, thereby eliminating the need for electrically conductive vias electrically connected to the power plane portion and the ground plane portion of the buried layer.
1. A method for eliminating electrically conductive vias in a multilayer circuit board, the multilayer circuit board having a top layer and a buried layer separated by at least one dielectric layer, the buried layer including an electrically conductive power plane portion and an electrically conductive ground plane portion, the method comprising the step of:
forming a cavity in the multilayer circuit board extending through the top layer and the at least one dielectric layer so as to expose at least a portion of the power plane portion and the ground plane portion of the buried layer within the cavity, wherein the cavity is sized to accommodate an electronic component therein such that the electronic component makes electrical contact with the exposed portion of the power plane portion and the ground plane portion of the buried layer, thereby eliminating the need for electrically conductive vias electrically connected to the power plane portion and the ground plane portion of the buried layer.
2. The method as defined in claim 1 , wherein the step of forming a cavity comprises the step of:
etching the cavity in the multilayer circuit board.
3. The method as defined in claim 2 , wherein the step of etching the cavity includes photolithographically etching the cavity in the multilayer circuit board.
4. The method as defined in claim 2 , wherein the step of etching the cavity includes plasma etching the cavity in the multilayer circuit board.
5. The method as defined in claim 1 , wherein the step of forming a cavity comprises the step of:
milling the cavity in the multilayer circuit board.
6. The method as defined in claim 5 , wherein the step of milling the cavity includes laser ablating the cavity in the multilayer circuit board.
7. The method as defined in claim 1 , wherein the step of forming a cavity comprises the step of:
prefabricating at least one of the top layer and the at least one dielectric layer such that the cavity is formed upon assembly of the top layer and the at least one dielectric layer in the multilayer circuit board.
8. The method as defined in claim 1 , wherein the electronic component is a first electronic component, wherein a second electronic component is mounted on the top layer, further comprising the step of:
extending at least one electrically conductive lead of the second electronic component into the cavity for electrical connection with the power plane portion or the ground plane portion of the buried layer.
9. The method as defined in claim 8 , wherein the cavity is a first cavity, wherein the at least one dielectric layer is at least one first dielectric layer, wherein an additional layer is disposed above and separated from the top layer by at least one second dielectric layer, further comprising the step of:
forming a second cavity in the multilayer circuit board extending through the additional layer and the at least one second dielectric layer so as to expose at least a portion of the top layer, wherein the second cavity is sized to accommodate the second electronic component therein.
10. The method as defined in claim 9 , further comprising the step of:
disposing an electrically conductive shield on the additional layer over the second cavity for shielding electromagnetic interference to and from the first and second electronic components.
11. A method for eliminating electrically conductive vias in a multilayer circuit board, the multilayer circuit board having a top layer and a buried layer separated by at least one dielectric layer, the buried layer including an electrically conductive power/ground plane portion, the method comprising:
forming a cavity in the multilayer circuit board extending through the top layer and the at least one dielectric layer so as to expose at least a portion of the power/ground plane portion of the buried layer within the cavity, wherein the cavity is sized to accommodate an electronic component therein such that the electronic component makes electrical contact with the exposed portion of the power/ground plane portion of the buried layer, thereby eliminating the need for electrically conductive vias electrically connected to the power/ground plane portion of the buried layer.
12. A method for eliminating electrically conductive vias in a multilayer circuit board, the multilayer circuit board having a top layer separated from a group of adjacent buried layers by at least one first dielectric layer, the group of buried layers including an electrically conductive power plane layer, an electrically conductive ground plane layer, and at least one second dielectric layer separating the power plane layer from the ground plane layer so as to form a buried bypass capacitor within the multilayer circuit board, the top layer supporting an electronic component thereon, the method comprising the step of:
forming a cavity in the multilayer circuit board extending through the top layer and the at least one first dielectric layer so as to expose at least a portion of the power plane layer within the cavity, wherein the cavity is sized to accommodate at least one extended electrically conductive lead of the electronic component for electrical connection with the power plane layer, thereby eliminating the need for electrically conductive vias electrically connected to the power plane layer.