Built-in self-test circuit
View Patent ↗A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.
1. A built-in self-test (BIST) circuit that is included in a large-scale integrated circuit (LSI) for testing a random-access memory (RAM) that outputs a plurality of bit sets each of which includes a plurality of bits, comprising:
a selector that is supplied with one of the bit sets and selects the bits in the bit set one by one;
a 1-bit comparator that compares a bit selected by the selector with expected value data;
a data generator that supplies the expected value data to the 1-bit comparator; and
a controller that controls the data generator to generate the expected value data, wherein
a pair of the selector and the 1-bit comparator is provided to each of the bit sets.
2. The BIST circuit according to claim 1 , wherein the controller includes a logic circuit that controls the selector to select a first bit in the bit set, and then select a second bit in the bit set after a test on the first bit is completed.
3. The BIST circuit according to claim 1 , wherein the selector selects two bits in the bit set one by one.
4. The built-in self-test (BIST) circuit according to claim 1 , further comprising a control terminal to which a control signal is input, wherein the control signal controls the selector to select a first bit in the bit set, and then select a second bit in the bit set after a test on the first bit is completed.
5. A built-in self-test (BIST) circuit that is included in a large-scale integrated circuit (LSI) for testing a random-access memory (RAM) that outputs a plurality of bit sets, each of which includes a plurality of bits, so that the bits in each of the bit sets are output through different ports of the RAM comprising:
a selector that is supplied with one of the bit sets and selects the bits in the bit set one by one;
a 1-bit comparator that compares a bit selected by the selector with expected value data;
a data generator that supplies the expected value data to the 1-bit comparator; and
a controller that controls the data generator to generate the expected value data, wherein
a pair of the selector and the 1-bit comparator is provided for each of the bit sets.
6. The BIST circuit according to claim 5 , wherein the controller includes a logic circuit that controls the selector to select a first bit in the bit set, and then select a second bit in the bit set after a test on the first bit is completed.
7. The BIST circuit according to claim 5 , wherein the selector selects two bits in the bit set one by one.
8. The built-in self-test (BIST) circuit according to claim 5 , further comprising a control terminal to which a control signal is input, wherein the control signal controls the selector to select a first bit in the bit set, and then select a second bit in the bit set after a test on the first bit is completed.
9. A built-in self-test (BIST) circuit that is included in a large-scale integrated circuit (LSI) for testing a random-access memory (RAM) that outputs a plurality of bit sets, each of which includes a plurality of bits, so that the bits in each of the bit sets are output through different ports of the RAM comprising:
a first selector that is supplied with a first bit set of the bit sets and selects the bits in the first bit set one by one;
a second selector that is supplied with a second bit set of the bit sets and selects the bits in the second bit set one by one;
a third selector that is connected to the first selector and the second selector and selects the bits selected by the first selector and the second selector one by one;
a 1-bit comparator that is connected to the third selector and compares a bit selected by the third selector with expected value data;
a data generator that supplies the expected value data to the 1-bit comparator; and
a controller that controls the data generator to generate the expected value data, wherein
a set of the first selector, the second selector, the third selector, and the 1-bit comparator is provided for every predetermined number of bit sets.
10. The BIST circuit according to claim 9 , wherein the controller includes a logic circuit that controls
the first selector to select a first bit in the first bit set,
the second selector to select a second bit in the second bit set,
the third selector to select the first bit and then select the second bit after a test on the first bit is completed,
the first selector to select a third bit in the first bit set after a test on the second bit is completed,
the second selector to select a fourth bit in the second bit set, and
the third selector to select the third bit, and then select the fourth bit after a test on the third bit is completed.
11. The BIST circuit according to claim 9 , wherein the first selector selects two bits in the first bit set one by one and the second selector selects two bits in the second bit set one by one.
12. The BIST circuit according to claim 9 , wherein the third selector selects two bits selected by the first selector and the second selector one by one.
13. The built-in self-test (BIST) circuit according to claim 9 , further comprising a control terminal to which a control signal is input, wherein the control signal controls
the first selector to select a first bit in the first bit set,
the second selector to select a second bit in the second bit set,
the third selector to select the first bit, and then select the second bit after a test on the first bit is completed,
the first selector to select a third bit in the first bit set after a test on the second bit is completed,
the second selector to select a fourth bit in the second bit set, and
the third selector to select the third bit, and then select the fourth bit after a test on the third bit is completed.