IP Library Granted Patent US 6,936,502
Granted Patent B2
US 6,936,502 · App. 10/437,006 · Granted Aug 30, 2005

Package modification for channel-routed circuit boards

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,936,502
App. No.
10/437,006
Granted
Aug 30, 2005
Kind
B2
Abstract

A method for implementing a circuit component on a surface of a multilayer circuit board is provided. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board.

Claims (13)

1. A method for implementing a circuit component on a surface of a multilayer circuit board, the method comprising the steps of:

providing the multilayer circuit board having a plurality of electrically conductive vias penetrating layers of the multilayer circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the multilayer circuit board beneath at least one of the plurality of electrically conductive vias; and

providing the circuit component having a plurality of pins, wherein at least one pin of the plurality of pins has a length that is formed to coincide with a depth of a corresponding via of the multilayer circuit board.

2. The method as in claim 1 , further comprising the step of:

joining the circuit component to the surface of the multilayer circuit board, wherein each pin of a subset of the plurality of pins extends into and is in electrical contact with a corresponding via of the multilayer circuit board.

3. The method as in claim 1 , wherein the circuit component includes a pre-existing component having a pin with a length greater than the depth of a corresponding via, and wherein the pin has a length that is formed to coincide with the depth of the corresponding via by trimming the pin to a length no greater than the depth of the corresponding via.

4. The method as in claim 1 , wherein the circuit component includes a circuit component that is fabricated specifically for use with the multilayer circuit board.

5. The method as in claim 4 , wherein the at least one pin is formed to have a length that coincides with the depth of a corresponding via according to the further method steps of:

inserting a plurality of pins into corresponding openings in a fixture, the openings having depths equivalent to corresponding vias of the multilayer circuit board, and wherein a portion of one or more of the plurality of pins extends above a surface of the fixture;

removing the portion of the one or more pins that extends above the surface of the fixture, wherein a remaining portion of each of the one or more pins has a length substantially equivalent to the depth of the corresponding opening; and

electrically connecting each remaining portion of the one or more pins to a corresponding input or output of the circuit component.

6. The method as in claim 1 , wherein each of a subset of the plurality of pins includes one of the group consisting of: a straight pin, a metal dendrite, a column, and a ball.

7. The method as in claim 1 , wherein the plurality of pins includes a combination of the group consisting of: a straight pin, a metal dendrite, a column, and a ball.

Assignments (5)
RELEASE (REEL 038041 / FRAME 0001) Recorded Jan 2, 2018
From: JPMORGAN CHASE BANK, N.A.
To: RPX CORPORATION; RPX CLEARINGHOUSE LLC
Reel/Frame 044970/0030 →
SECURITY AGREEMENT Recorded Mar 9, 2016
From: RPX CORPORATION; RPX CLEARINGHOUSE LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038041/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2015
From: ROCKSTAR CONSORTIUM US LP; ROCKSTAR CONSORTIUM LLC; BOCKSTAR TECHNOLOGIES LLC; CONSTELLATION TECHNOLOGIES LLC; MOBILESTAR TECHNOLOGIES LLC; NETSTAR TECHNOLOGIES LLC
To: RPX CLEARINGHOUSE LLC
Reel/Frame 034924/0779 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2014
From: ROCKSTAR BIDCO, LP
To: ROCKSTAR CONSORTIUM US LP
Reel/Frame 032425/0867 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2011
From: NORTEL NETWORKS LIMITED
To: ROCKSTAR BIDCO, LP
Reel/Frame 027164/0356 →