Circuit for driving plasma display panel
View Patent ↗In a circuit for driving a plasma display panel including a first circuit formed on a scanning substrate for driving a scanning electrode, and a second circuit formed on a common substrate for driving a common electrode, the circuit in accordance with the present invention is characterized by including a single substrate in place of the scanning and common substrates wherein the first and second circuits are formed on the single substrate.
1. A circuit for driving a plasma display panel comprising:
a first circuit for driving a scanning electrode of said plasma display panel;
a second circuit for driving a common electrode of said plasma display panel;
a single substrate on which said first circuit and said second circuit are formed;
a relay substrate arranged between said second circuit and said plasma display panel to electrically connect said second circuit to said common electrode; and
a waveform-shaping slice diode mounted on said relay substrate for reducing overshoot of an output signal of said second circuit.
2. The circuit as set forth in claim 1 , further comprising a ground line formed on said single substrate for electrically connecting a first clamp circuit associated with said first circuit and a second clamp circuit associated with said second circuit to each other.
3. The circuit as set forth in claim 1 , wherein said waveform-shaping slice diode is located in the vicinity of an edge of said plasma display panel.
4. A circuit for driving a plasma display panel comprising:
a first circuit for driving a scanning electrode of said plasma display panel;
a second circuit for driving a common electrode of said plasma display panel;
a single substrate on which said first circuit and said second circuit are formed;
a relay substrate arranged between said first circuit and said plasma display panel to electrically connect said first circuit to said scanning electrode; and
a waveform-shaping slice diode mounted on said relay substrate for reducing overshoot of an output signal of said first circuit.
5. The circuit as set forth in claim 4 , wherein said waveform-shaping slice diode is located in the vicinity of an edge of said plasma display panel.
6. A circuit for driving a plasma display panel, comprising:
a first circuit for driving a scanning electrode of said plasma display panel, said first circuit including a third circuit for collecting electric charges, said third circuit including a single capacitor for accumulating electric charges therein;
a second circuit for driving a common electrode of said plasma display panel, said second circuit including a fourth circuit for collecting electric charges, said fourth circuit including said single capacitor in common with said third circuit;
a single substrate on which said first and second circuits are formed;
a relay substrate arranged between said second circuit and said plasma display panel to electrically connect said second circuit to said common electrode; and
a waveform-shaping slice diode mounted on said relay substrate for reducing overshoot of an output signal of said second circuit.
7. The circuit as set forth in claim 6 , further comprising a ground line formed on said single substrate for electrically connecting a first clamp circuit associated with said first circuit and a second clamp circuit associated with said second circuit to each other.
8. The circuit as set forth in claim 6 , further comprising a V s reverse circuit used commonly by said first and second circuits.
9. The circuit as set forth in claim 6 , further comprising a V s clamp circuit used commonly by said first and second circuits.
10. The circuit as set forth in claim 6 , wherein said waveform-shaping slice diode is located in the vicinity of an edge of said plasma display panel.
11. A circuit for driving a plasma display panel, comprising:
a first circuit for driving a scanning electrode of said plasma display panel, said first circuit including a third circuit for collecting electric charges, said third circuit including a single capacitor for accumulating electric charges therein;
a second circuit for driving a common electrode of said plasma display panel, said second circuit including a fourth circuit for collecting electric charges, said fourth circuit including said single capacitor in common with said third circuit;
a single substrate on which said first and second circuits are formed;
a relay substrate arranged between said first circuit and said plasma display panel to electrically connect said first circuit to scanning electrode; and
a waveform-shaping slice diode mounted on said relay substrate for reducing overshoot of an output signal of said first circuit.
12. The circuit as set forth in claim 11 , wherein said waveform-shaping slice diode is located in the vicinity of an edge of said plasma display panel.
13. A circuit for driving a plasma display panel comprising:
a first circuit for driving a scanning electrode of said plasma display panel;
a second circuit for driving a common electrode of said plasma display panel;
a third circuit for collecting electric charges, wherein said third circuit connects said first circuit and said second circuit to each other therethrough;
a relay substrate which is arranged facing a rear surface of said plasma display panel to electrically connect said second circuit to said common electrode;
a single substrate on which said first circuit, said second circuit, and said third circuit are formed,
said single substrate being arranged facing the rear surface of said plasma display panel,
a first end of said single substrate being electrically connected to a first end of said plasma display panel,
a second end of said single substrate being electrically connected to a second end of said plasma display panel through said relay substrate; and
a waveform-shaping slice diode mounted on said relay substrate for reducing overshoot of an output signal of said second circuit.
14. The circuit as set forth in claim 13 , wherein said connector substrate comprises:
a first substrate arranged facing the second end of said plasma display panel; and
a second substrate mechanically and electrically connecting said single substrate and said first substrate to each other.
15. The circuit as set forth in claim 13 , further comprising a ground line formed on said single substrate for electrically connecting a first clamp circuit associated with said first circuit and a second clamp circuit associated with said second circuit to each other.
16. The circuit as set forth in claim 13 , wherein said waveform-shaping slice diode is located in the vicinity of an edge of said plasma display panel.
17. A circuit for driving a plasma display panel, comprising:
a first circuit for driving a scanning electrode of said plasma display panel;
a second circuit for driving a common electrode of said plasma display panel;
a third circuit for collecting electric charges, wherein said third circuit connects said first circuit and said second circuit to each other therethrough;
a relay substrate which is arranged facing a rear surface of said plasma display panel to electrically connect said first circuit to said scanning electrode;
a single substrate on which said first circuit, said second circuit, and said third circuit are formed, said single substrate being arranged facing the rear surface of said plasma display panel, a first end of said single substrate being electrically connected to a first end of said plasma display panel, and a second end of said single substrate being electrically connected to a second end of said plasma display panel through said relay substrate; and
a waveform-shaping slice diode mounted on said relay substrate for reducing overshoot of an output signal of said first circuit.
18. The circuit as set forth in claim 17 , wherein said waveform-shaping slice diode is located in the vicinity of an edge of said plasma display panel.
19. A circuit for driving a plasma display panel comprising:
a first circuit for driving a scanning electrode;
a second circuit for driving a common electrode; and
a single capacitor for accumulating electric charges from said first circuit and said second circuit;
wherein said first circuit, said second circuit, and said single capacitor are formed on a single substrate.
20. The circuit as set forth in claim 19 , further comprising a ground line formed on said single substrate for electrically connecting a first clamp circuit associated with said first circuit and a second clamp circuit associated with said second circuit to each other.
21. The circuit as set forth in claim 19 , further comprising a waveform-shaping slice diode.