Digital adjustment of gain and offset for digital to analog converters
View Patent ↗Improved digital to analog converter (DAC) circuitry incorporating the ability to utilize a single DAC to generate either voltage or current outputs, and the ability to digitally adjust the gain and offset. Previous digital to analog circuitry has been limited to a single type of analog output per DAC and to the use of external precision resistors to set the gain and offset for a single DAC, or a group of DACs. By utilizing the same on-chip circuitry to supply both types of outputs, chip area, power consumption and cost is reduced while offering more flexibility to the customer. The ability to digitally adjust the gain and offset for a group of DACs eliminates the cost of external resistors, lowers the board area, and lowers the assembly cost for the end product. In addition, since gain and offset can be adjusted dynamically, maximum flexibility is provided to the customer. Digital adjustment of gain and offset can be used to calibrate for chip and system errors, and can allow more exact adjustment and external precision resistors.
1. An integrated circuit for adjusting the gain of a digital-to-analog converter comprising:
a secondary digital-to-analog converter receiving a digital input value and producing an analog signal having current corresponding to said digital input value;
a first current mirror circuit coupled to said secondary digital-to-analog converter and producing matching first and second current outputs corresponding to said analog signal, said first current output providing a current gain adjustment signal for said digital-to-analog converter;
a second current mirror circuit coupled to said first current mirror circuit and producing a current output matching said second current output of said first current mirror circuit; and
a resistor coupled to said current output of said second current mirror circuit and providing a voltage gain adjustment signal for said digital-to-analog converter;
wherein, said current gain adjustment signal and said voltage gain adjustment signal are determined by said integrated circuit without external resistors.
2. The integrated circuit of claim 1 , wherein said secondary digital-to-analog converter further receives at least one of a current gain input signal and a voltage gain input signal.
3. The integrated circuit of claim 2 , wherein said secondary digital-to-analog converter further receives a mode input for selecting between said current gain input signal and said voltage gain input signal.
4. The integrated circuit of claim 2 , further comprising an amplifier circuit providing said current gain input signal and said voltage gain input signal.
5. The integrated circuit of claim 1 , wherein said resistor is internal to said integrated circuit.
6. The integrated circuit of claim 1 , wherein said digital input value comprises a thirteen-bit digital value.
7. The integrated circuit of claim 1 , wherein said secondary digital-to-analog converter comprises a current steering digital-to-analog converter.
8. An integrated circuit for adjusting the offset of a digital-to-analog converter comprising:
a secondary digital-to-analog converter receiving a digital input value and producing an analog signal having current corresponding to said digital input value;
a first current mirror circuit coupled to said secondary digital-to-analog converter and producing matching first and second current outputs corresponding to said analog signal, said first current output providing a current offset adjustment signal for said digital-to-analog converter;
a resistor coupled to said second current output of said current mirror circuit and providing a voltage offset adjustment signal for said digital-to-analog converter; and
a second current mirror circuit coupled to said first current mirror circuit and receiving a master current input; and
wherein, said current offset adjustment signal and said voltage offset adjustment signal are determined by said integrated circuit without external resistors.
9. The integrated circuit of claim 8 , wherein said secondary digital-to-analog converter further receives at least one of a current offset input signal and a voltage offset input signal.
10. The integrated circuit of claim 9 , wherein said secondary digital-to-analog converter further receives a mode input for selecting between said current offset input signal and said voltage offset input signal.
11. The integrated circuit of claim 9 , further comprising an amplifier circuit providing said current offset input signal and said voltage offset input signal.
12. The integrated circuit of claim 8 , wherein said resistor is internal to said integrated circuit.
13. The integrated circuit of claim 8 , wherein said digital input value comprises a thirteen-bit digital value.
14. The integrated circuit of claim 8 , wherein said secondary digital-to-analog converter comprises a current steering digital-to-analog converter.
15. An integrated circuit for adjusting the gain and offset of a digital-to-analog converter comprising:
a gain control circuit including a secondary digital-to-analog converter receiving a digital input value and producing an analog signal having current corresponding to said digital input value, a first current mirror circuit coupled to said secondary digital-to-analog converter and producing matching first and second current outputs corresponding to said analog signal, said first current output providing a current gain adjustment signal for said digital-to-analog converter, a second current mirror circuit coupled to said first current mirror circuit and producing a current output matching said second current output of said first current mirror circuit, and a resistor coupled to said current output of said second current mirror circuit and providing a voltage gain adjustment signal for said digital-to-analog converter;
an offset control circuit including a secondary digital-to-analog converter receiving a digital input value and producing an analog signal having current corresponding to said digital input value, a current mirror circuit coupled to said secondary digital-to-analog converter and producing matching first and second current outputs corresponding to said analog signal, said first current output providing a current offset adjustment signal for said digital-to-analog converter, a resistor coupled to said second current output of said current mirror circuit and providing a voltage offset adjustment signal for said digital-to-analog converter, and a second current mirror circuit coupled to said first current mirror circuit and receiving a master current input;
wherein, said current gain adjustment signal, said voltage gain adjustment signal, said current offset adjustment signal, and said voltage offset adjustment signal are determined by said integrated circuit without external resistors.
16. The integrated circuit of claim 15 , wherein said secondary digital-to-analog converter of said gain control circuit further receives at least one of a current gain input signal and a voltage gain input signal.
17. The integrated circuit of claim 16 , wherein said secondary digital-to-analog converter of said gain control circuit further receives a mode input for selecting between said current gain input signal and said voltage gain input signal.
18. The integrated circuit of claim 16 , wherein said gain control circuit further comprising an amplifier circuit providing said current gain input signal and said voltage gain input signal.
19. The integrated circuit of claim 15 , wherein said secondary digital-to-analog converter of said offset control circuit further receives at least one of a current offset input signal and a voltage offset input signal.
20. The integrated circuit of claim 19 , wherein said secondary digital-to-analog converter of said offset control circuit further receives a mode input for selecting between said current offset input signal and said voltage offset input signal.
21. The integrated circuit of claim 19 , wherein said offset control circuit further comprising an amplifier circuit providing said current offset input signal and said voltage offset input signal.
22. The integrated circuit of claim 15 , wherein said resistor of said gain control circuit and said resistor of said offset control circuit are internal to said integrated circuit.
23. The integrated circuit of claim 15 , wherein said digital input value to said gain control circuit comprises a thirteen-bit digital value.
24. The integrated circuit of claim 15 , wherein said secondary digital-to-analog converter of said gain control circuit comprises a current steering digital-to-analog converter.
25. The integrated circuit of claim 15 , wherein said resistor of said offset control circuit is internal to said integrated circuit.
26. The integrated circuit of claim 15 , wherein said digital input value to said offset control circuit comprises a thirteen-bit digital value.
27. The integrated circuit of claim 15 , wherein said secondary digital-to-analog converter of said offset control circuit comprises a current steering digital-to-analog converter.