Liquid crystal display device having indented gate electrode and fabricating method thereof

1. An array substrate for a liquid crystal display device, comprising:

a substrate;

a gate line on the substrate;

a data line crossing the gate line to define a pixel region;

a thin film transistor connected to the gate line and the data line, and includes a gate electrode having opposing first and second edges and only the first edge including an indented portion, an active layer, an ohmic contact layer, and a source and a drain electrodes; wherein

the drain electrode overlapping the indented portion, and

the source electrode overlapping the second edge of the gate electrode,

the indented portion of the first edge has a substantially “V” shape such that

the vertex of the substantially “V” shaped indented portion corresponds to a center of the overlapping drain electrode; and

a pixel electrode connected to the thin film transistor, and disposed in, the pixel.

2. The substrate according to claim 1 , wherein the gate electrode protrudes from the gate line to define a first length of the gate electrode along a direction of the data line, and the source electrode protrudes from the data line.

3. The substrate according to claim 2 , wherein the active layer and the ohmic contact layer extend under the data line.

4. The substrate according to claim 3 , wherein the active layer includes amorphous silicon and the ohmic contact layer includes impurity-doped amorphous silicon.

5. The substrate according to claim 1 , wherein the indented portion has a second length along the direction of the data line that is shorter than the first length and longer than about 4 μm.

6. A fabricating method of an array substrate for a liquid crystal display device, comprising:

forming a gate line and a gate electrode on a substrate, the gate electrode having opposing first and second edges and only the first edge includes a indented portion;

forming a gate insulating layer on the gate line and the gate electrode;

forming an active layer on the gate insulating layer;

forming an ohmic contact layer on the active layer;

forming a data line and a source and a drain electrodes on the ohmic contact layer, the data line crossing the gate line to define a pixel region, the drain electrode overlapping the gate electrode at the first edge and the source electrode overlapping the gate electrode at the second side edge, wherein the indented portion has a substantially “V” shape such that the vertex of the substantially “V” shaped indented portion corresponds to a center of the overlapping drain electrode;

forming a passivation layer on the data line and the source and drain electrodes, the passivation layer having a drain contact hole exposing the drain electrode; and

forming a pixel electrode at the pixel region, and connected to the drain electrode through the drain contact hole.

7. The method according to claim 6 , wherein the gate electrode protrudes from the gate line, along the first side edge to define a first length, and the source electrode protrudes from the data line.

8. The method according to claim 7 , wherein the active layer and the ohmic contact layer extend under the data line.

9. The method according to claim 8 , wherein the active layer includes amorphous silicon and the ohmic contact layer includes impurity-doped amorphous silicon.

10. The method according to claim 6 , wherein the indented portion has a second length along a direction of the data line that is shorter than the first length and longer than about 4 μm.

11. A thin film transistor, comprising:

a substrate;

a gate electrode on the substrate having opposing first and second edges and only the first side edge including a indented portion;

an active layer over the gate electrode; and source and drain electrodes over the active layer, the drain electrode overlapping the gate electrode at the first side edge and the source electrode overlapping the gate electrode at the second edge, wherein the indented portion has a substantially “V” shape such the vertex of the substantially “V” shaped indented portion corresponds to a center of the overlapping drain electrode.

12. The transistor according to claim 11 , wherein the indented portion has a substantially “V” shape.

13. The transistor according to claim 12 , wherein the first side has a first length and the indented portion has a second length shorter than the first length and longer than about 4 μm.