Asymmetric memory cell

1. A method for forming an asymmetric memory cell, the method comprising:

forming a bottom electrode having a first contact area;

forming an electrical pulse various resistance (EPVR) material overlying the bottom electrode first contact area;

forming a top electrode overlying the EPVR layer having a second area in contact with the EPVR material, less than the first contact area.

2. The method of claim 1 further comprising:

inducing an electric field between the top electrode and the bottom electrode; and,

in response to the electric field, inducing current flow through the EPVR adjacent the top electrode.

3. The method of claim 2 further comprising:

in response to inducing current flow through the EPVR adjacent the top electrode, modifying the resistance of the EPVR between the top and bottom electrodes.

4. The method of claim 3 wherein inducing an electric field between the top electrode and the bottom electrode includes applying a negative voltage pulse between the top and bottom electrodes having an amplitude in the range of 2 to 5 volts and a time duration in the range of 1 nanosecond (ns) to 10 microseconds (μs); and,

wherein modifying the resistance of the EPVR between the top and bottom electrodes includes creating a first, high resistance between the electrodes.

5. The method of claim 4 wherein inducing an electric field between the top electrode and the bottom electrode includes applying a positive pulse between the top and bottom electrodes having an amplitude in the range of 2 to 5 volts and a time duration in the range of 1 ns to 10 μs; and,

wherein modifying the resistance of the EPVR between the top and bottom electrodes includes creating a second resistance between the electrodes, lower than the first resistance.

6. The method of claim 3 wherein modifying the resistance of the EPVR between the top and bottom electrodes in response to inducing current flow through the EPVR adjacent the top electrode includes modifying the resistance within the range of 100 ohms to 10 mega-ohms.

7. The method of claim 1 wherein forming a top electrode overlying the EPVR layer having a second contact area, less than the first contact area, includes the second contact area being at least 20% smaller than the first contact area.

8. The method of claim 1 wherein forming a bottom electrode includes forming the bottom electrode from a material selected from the group including Pt, TiN, TaN, TiAlN, TaAlN, Ag, Au, and Ir; and,

wherein forming a top electrode includes forming the top electrode from a material selected from the group including Pt, TiN, TaN, TiAlN, TaAlN, Ag, Au, and Ir.

9. The method of claim 1 wherein forming an EPVR layer includes forming an EPVR layer from a material selected from the group including colossal magnetoresistance (CMR), high temperature super conducting (HTSC), and perovskite metal oxide materials.

10. A method for forming an asymmetric memory cell, the method comprising:

forming a bottom electrode having a first contact area;

forming an electrical pulse various resistance (EPVR) material overlying the bottom electrode first contact area;

forming a top electrode overlying the EPVR layer having a second area in contact with the EPVR material, greater than the first contact area.

11. The method of claim 10 wherein forming a top electrode overlying the EPVR layer having a second contact area, greater than the first contact area, includes the first contact area being at least 20% smaller than the second contact area.

12. An asymmetric memory cell comprising:

a bottom electrode having a first contact area;

an electrical pulse various resistance (EPVR) material layer overlying the bottom electrode first contact area; and,

a top electrode overlying the EPVR layer having a second area in contact with the EPVR materials, less than the first contact area.

13. The memory cell of claim 12 wherein the top electrode second contact area is at least 20% less than the bottom electrode first contact area.

14. The memory cell of claim 13 wherein the bottom electrode is a material selected from the group including Pt, TiN, TaN, TiAlN, TaAlN, Ag, Au, and Ir; and,

wherein the top electrode is a material selected from the group including Pt, TIN, TaN, TiAlN, TaAlN, Ag, Au, and Ir.

15. The memory cell of claim 13 wherein the EPVR layer has a first overall resistance, as measured between the top and bottom electrodes, responsive to a first voltage pulse, applied between the top and bottom electrodes; and,

wherein the EPVR layer has a second overall resistance, less than the first resistance, responsive to a second voltage pulse.

16. The memory cell of claim 15 wherein the EPVR layer first resistance is in the range of 100 ohms to 10 mega-ohms, responsive to the first voltage pulse having an negative amplitude in the range of 2 to 5 volts and a time duration in the range of 1 nanosecond (ns) and 10 microseconds (μs).

17. The memory cell of claim 16 wherein the EPVR layer second resistance is in the range of 100 ohms to 1 kohm, responsive to the second voltage pulse having an positive amplitude in the range of 2 to 5 volts and a time duration in the range of 1 ns to 10 μs.

18. The memory cell of claim 12 wherein the EPVR layer is a material selected from the group including colossal magnetoresistance (CMR), high temperature super conducting (HTSC), and perovskite metal oxide materials.

19. An asymmetric memory cell comprising:

a bottom electrode having a first contact area;

an electrical pulse various resistance (EPVR) material layer overlying the bottom electrode first contact area; and,

a top electrode overlying the EPVR layer having a second area in contact with the EPVR material, greater than the first contact area.

20. The memory cell of claim 19 wherein the bottom electrode first contact area is at least 20% less than the top electrode second contact area.