Synchronous OTDM: gapped clock creation and duty cycle multiplication

1. A method of combining N input NRZ optical data signals, each having an equal bit period and duty cycle, into one time-division multiplexed output signal, comprising:

providing N synchronized input NRZ signals;

shortening the pulse width of each input signal by reducing the duty cycle by a factor of 1/N while keeping the bit period the same;

delaying said shortened input signals one from another by a fixed delay such that all N signals occur within one said bit period; and

combining said delayed N shortened signals to form one multiplexed output signal,

wherein N is an integer greater than 1 and is equal to the number of signals being combined; and

wherein said shortening of the pulse width while keeping the bit period the same comprises: AND-ing the input signal with a gap clock signal, where said gap clock signal has a pulse width equal to 1/N of the bit period of the input signal, and a bit period equal to that of the input signal.

2. A method of transforming a clock signal into a gap clock signal, where the gap clock signal has a pulse width of 1/N that of the clock signal and an overall bit period equal to that of the clock signal, where N is an even number, comprising:

a. XOR-ing the clock signal with a copy of the clock signal delayed by half of a pulse width to create a first intermediate signal;

b. AND-ing the first intermediate signal with the clock signal to create a second intermediate signal;

c. AND-ing the second intermediate signal with a copy of itself delayed by one half of its pulse width to create an output signal; and

repeating step (c) on its output signal until the clock signal's pulse width has been reduced by a factor of N.

3. A method of combining N input NRZ optical data signals, each having an approximately equal pulse width and period P, into one time-division multiplexed output signal, comprising:

providing N synchronized input NRZ signals, wherein N is an integer greater than 1 and is equal of the number of signals being combined;

shortening the pulse width of each input signal by a factor of 1/N while keeping the bit period the same;

introducing delays between successive ones of the input signals such that each period P includes one pulse from each of the input signals; and

interleaving the input signals to form one multiplexed output signal,

wherein the step of shortening of the pulse width while keeping the bit period the same comprises: AND-ing the input signal with a gap clock signal, where said gap clock signal has a pulse width equal to 1/N of the bit period of the input signal, and a bit period equal to that of the input signal.