Monolithic read-while-write flash memory device

1. A memory device comprising:

a random-access flash cell array that includes an executable flash device portion configured for random-access;

a serial-access flash cell array that includes a non-executable flash device portion configured for serial-access, wherein the random-access flash cell array and the serial-access flash cell array are both fabricated on a common die using insulating floating gate technology;

first circuitry for managing the executable flash device portion; and

second circuitry for managing the non-executable flash device portion, wherein the second circuitry is configured to perform at least one of a write operation and an erase operation in the non-executable flash device portion simultaneously with a processor executing code in the executable flash device portion;

wherein the first circuitry and the second circuitry are all located on the common die; and

wherein the second circuitry occupies a smaller area per cell on the common die than the first circuitry occupies per cell on the common die.

2. The memory device of claim 1 , wherein the executable flash device portion and the non-executable flash device portion have a common flash memory cell structure.

3. The memory device of claim 2 , wherein the flash memory cell structure includes an insulating floating gate.

4. An electronic device comprising the memory device of claim 1 .

5. The electronic device of claim 4 , wherein the electronic device is a cellular telephone.

6. The electronic device of claim 4 , wherein the electronic device is a personal data assistant.

7. The memory device of claim 1 , wherein the executable flash device portion occupies a first area on the common die that is smaller than a second area occupied on the common die by the non-executable flash device portion.

8. The memory device of claim 1 , wherein the executable flash device portion is configured to permit the processor to execute the code in-place without the code first being copied to another memory device.

9. A method of operating an electronic device, the method comprising:

in a memory device that includes:

a random-access flash cell array that includes an executable flash device portion configured for random-access;

a serial-access flash cell array that includes a non-executable flash device portion configured for serial-access, wherein the random-access flash cell array and the serial-access flash cell array are fabricated on a common die using insulating floating gate technology;

first circuitry for managing the executable flash device portion; and

second circuitry for managing the non-executable flash device portion;

wherein the first circuitry and the second circuitry are located on the common die and wherein the second circuitry occupies a smaller area per cell on the common die than the first circuitry occupies per cell on the common die, performing:

executing code for operating the electronic device in-place, wherein the code for operating the electronic device is stored only in the executable flash device portion and wherein the code for operating the electronic device is executed simultaneously with the second circuitry performing at least one of a write operation and an erase operation in the non-executable flash device portion.

10. The method of claim 9 , wherein the executable flash device portion occupies a first area on the common die that is smaller than a second area occupied on the common die by the non-executable flash device portion.

11. An electronic device comprising a memory device that includes:

a random-access flash cell array that includes an executable flash device portion configured for random-access, the executable flash device portion having stored therein code for operating the electronic device;

a serial-access flash cell array that includes a non-executable flash device portion configured for serial-access, wherein the random-access flash cell array and the serial-access flash cell array are fabricated on a common die using insulating floating gate technology;

first circuitry for managing the executable flash device portion; and

second circuitry for managing the non-executable flash device portion, wherein the second circuitry is configured to perform at least one of a write operation and an erase operation in the non-executable flash device portion simultaneously with a processor executing the code for operating the electronic device stored in the executable flash device portion;

wherein the first circuitry and the second circuitry are located on the common die; and

wherein the second circuitry occupies a smaller area per cell on the common die than the first circuitry occupies per cell on the common die.

12. The electronic device of claim 11 , wherein the executable flash device portion occupies an area on the common die that is smaller than an area occupied on the common die by the non-executable flash device portion.

13. A memory device comprising:

an array that includes a random-access flash cell portion and a serial-access flash cell portion that are both fabricated on a common die using insulating floating gate technology;

first circuitry for managing the random-access flash cell portion as a random-access executable portion; and

second circuitry for managing the serial-access flash cell portion as a serial-access non-executable portion, wherein the second circuitry is configured to perform at least one of a write operation and an erase operation in the serial-access flash cell portion simultaneously with a processor executing code in the random-access flash cell portion;

wherein the array, the first circuitry and the second circuitry all are located on the common die; and

wherein the first circuitry occupies a larger area per cell on the common die than the second circuitry occupies per cell on the common die.

14. The memory device of claim 13 , wherein the random-access flash cell portion and the serial-access flash cell portion comprise flash memory cells, wherein each flash memory cell has a common flash memory cell structure.

15. The memory device of claim 14 , wherein each of the flash memory cells has a corresponding insulated floating gate.

16. The memory device of claim 14 , wherein each of the flash memory cells is structured as a random-access flash cell.

17. The memory device of claim 13 , wherein the random-access flash cell portion and the serial-access flash cell portion comprise flash memory cells, wherein each flash memory cell of the random-access flash cell portion is structured as a random-access flash cell and wherein each flash memory cell of the serial-access flash cell portion is structured as a serial-access flash cell.

18. The memory device of claim 13 , wherein the random-access flash cell portion and the serial-access flash cell portion comprise flash memory cells, wherein each flash memory cell of the random-access flash cell portion has a first memory structure and each flash memory cell of the serial-access flash cell portion has a second memory structure that differs from the first memory structure.

19. The memory device of claim 18 , wherein the first memory structure is a random-access flash memory structure and wherein the second memory structure is a serial-access flash memory structure.

20. The memory device of claim 19 , wherein the random-access flash memory structure is a NOR flash memory structure and wherein the serial-access flash memory structure is a NAND flash memory structure.

21. An electronic device comprising the memory device of claim 13 .

22. The electronic device of claim 21 , wherein the electronic device is at least one of a personal data assistant and a cellular telephone.

23. A method of operating an electronic device, the method comprising:

in a memory device that includes, on a common die:

an array that includes a random-access flash cell portion and a serial-access flash cell portion that are both fabricated on the common die using insulating floating gate technology;

first circuitry for managing the random-access flash cell portion of the array as a random-access executable portion; and

second circuitry for managing the serial-access flash cell portion of the array as a serial-access non-executable portion, wherein the second circuitry is configured to perform at least one of a write operation and an erase operation in the serial-access flash cell portion simultaneously with a processor executing code in the random-access flash cell portion;

wherein the first circuitry occupies a larger area per cell on the common die than the second circuitry occupies per cell on the common die;

storing, the code in the random-access flash cell portion, wherein the code is for operating the electronic device; and

executing the code in-place to operate the electronic device.

24. A method of operating an electronic device, the method comprising:

in a memory device that includes:

a random-access flash cell array that includes an executable flash device portion configured for random-access; and

a serial-access flash cell array that includes a non-executable flash device portion configured for serial-access, wherein the random-access flash cell array and the serial-access flash cell array are both fabricated on a common die using insulating floating gate technology;

wherein the executable flash device portion occupies a smaller area per cell of the common die than the non-executable flash device portion per cell of the common die,

simultaneously:

executing in-place code to operate the electronic device in the executable flash device portion; and

performing one of writing and erasing data in the non-executable flash device portion;

wherein the code to operate the electronic device is stored only in the executable flash device portion.

25. A method of operating an electronic device, the method comprising:

in a memory device that includes, on a common die:

an array that includes a random-access flash cell portion and a serial-access flash cell portion that are both fabricated on the common die using insulating floating gate technology;

first circuitry for managing the random-access flash cell portion of the array as a random-access executable portion; and

second circuitry for managing the serial-access flash cell portion of the array as a serial-access non-executable portion, wherein the second circuitry is configured to perform at least one of a write operation and an erase operation within the serial-access flash cell portion, wherein the first circuitry occupies a larger area per cell on the common die than the second circuitry occupies per cell on the common die, performing:

storing, in the random-access flash cell portion, code for operating the electronic device; and

simultaneously executing the code for operating the electronic device and performing at least one of the write operation and the erase operation.