Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium

1. A method of fabricating a semiconductor device, the method comprising:

forming a trench region in a single crystal silicon-germanium layer of a semiconductor substrate containing the single crystal silicon-germanium layer on the surface;

forming a first single crystal silicon layer in the trench region and on the single crystal silicon-germanium layer in an active region;

forming a first thermal oxide layer on the surface of the first single crystal silicon layer;

embedding an insulator in the trench region, thereby forming a device isolation region; and

forming a device in the active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

2. The method of claim 1 , wherein the first single crystal silicon layer is formed by epitaxial growth.

3. The method of claim 1 , wherein the insulator is a lamination of a silicon nitride layer and a silicon dioxide layer.

4. The method of claim 2 , wherein the insulator is a lamination of a silicon nitride layer and a silicon dioxide layer.

5. The method of claim 1 , wherein the semiconductor substrate is a single crystal silicon wafer, and wherein the single crystal silicon-germanium layer is a graded profile layer epitaxially formed from the single crystal silicon wafer towards the surface with a varied germanium ratio.

6. The method of claim 1 , wherein the step of forming the device isolation region includes:

forming a silicon nitride layer over the first thermal oxide layer;

depositing a silicon dioxide layer over the silicon nitride layer;

leveling the silicon dioxide layer by chemical-mechanical polishing by using the silicon nitride layer in the active region as a mechanical stopper; and

removing the silicon nitride layer.

7. The method of claim 1 , wherein the step of forming the device in the active region further includes:

forming well regions on the active region;

forming gate dielectrics on the first single crystal silicon layer;

forming gate polycrystalline silicon on the gate dielectric layer;

forming a gate side wall structure; and

forming source drain regions.

8. The method of claim 1 , further comprising forming a trench region in a silicon-germanium layer on the semiconductor substrate, wherein a silicon film in contact with the silicon-germanium layer is interposed between the dielectric filled inside the trench region and a silicon-germanium layer on the bottom and side walls of the trench region.