A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
1. A method of operating a cache memory arranged between a processor and a main memory of a computer, wherein, when the processer requests an item from main memory using an address in main memory for said item and that item is not held in the cache memory, said item is fetched from the main memory and loaded into one of a plurality of addressable storage locations in the cache memory, the addressable storage locations being arranged as a set of cache partitions and wherein each address includes a multi-bit partition selector identifying into which cache partition the item may be loaded so that one of said cache partitions is allocated to said item in dependence on the address of said item in main memory, said partition selector defining a number of cache partitions into which the cache is divisible, wherein the number of cache partitions is alterable during operation of the cache.
2. A method according to claim 1 , each address in main memory comprises a page number and a line-in-page number and wherein a plurality of processes are held in the main memory, each process including one or more sequence of instructions held at addresses in main memory with a common page number.
3. A method according to claim 2 , wherein one of said cache partitions is allocated to a process by associating said one cache partition with page numbers of that process in the main memory.
4. A method according to claim 1 , wherein the number of addressable storage locations in each cache partition is alterable.
5. A method according to claim 1 , wherein the association of cache partitions to page numbers is alterable while a process using these page numbers is being run by the processor.
6. A cache memory to operate between a processor and a main memory of a computer, the cache memory including a number of cache partitions, each cache partition having a size, the size of each cache partition and the number of cache partitions being alterable based on a number of processes pending for execution in the processor, wherein one of said cache partitions is allocated to a process by associating said one cache partition with page numbers of that process in the main memory.
7. The cache memory of claim 6 , wherein the number of cache partitions ranges from one to sixteen.
8. The cache memory of claim 6 , wherein each of said cache partitions includes a number of addressable storage locations and wherein the number of addressable storage locations in each cache partition is alterable.