Schemes for determining whether all of the fragments of a datagram are received
View Patent ↗Schemes for determining whether all of the fragments of a datagram are received are described herein. The schemes described herein can allocate fifteen bits of memory to one or more counters to facilitate a determination of whether all of the fragments of a datagram are received.
1. A method for determining whether, for a datagram fragmented into at least two fragments, the at least two fragments are received, the method comprising:
allocating memory to
a first counter value representing whether a final fragment is received, the first counter value based on more-fragments flags associated with the received at least two fragments, and
a second counter value representing receipt of a number of eight byte data units in the received at least two fragments,
based on the more-fragments flag associated with each received fragment,
determining that a received fragment is the final fragment and adjusting the first counter value by one and adjusting the second counter value by the fragment offset of the final fragment, or
determining that a received fragment is not the final fragment and adjusting the second counter value by the number of eight byte data units comprised in the received fragment, and
based on the first counter value being different than an initial first counter value and the second counter value being equal to an initial second counter value, determining whether the at least two fragments are received.
2. The method of claim 1 , wherein allocating comprises allocating fifteen bits of memory.
3. The method of claim 1 , wherein adjusting the first counter value comprises one of:
incrementing the first counter value by one, and
decrementing the first counter value by one.
4. The method of claim 1 , wherein adjusting the second counter value by the fragment offset of the final fragment comprises one of:
incrementing the second counter value by the fragment offset, and
decrementing the second counter value by the fragment offset.
5. The method of claim 1 , wherein adjusting the second counter value by the number of eight byte data units comprised in the at least one fragment comprises one of:
incrementing the second counter value by the number of eight byte data units comprised in the at least one fragment, and
decrementing the second counter value by the number of eight byte data units comprised in the at least one fragment.
6. The method of claim 1 , wherein the initial second counter value comprises 2 13 .
7. The method of claim 1 , wherein the second counter comprises a sign.
8. The method of claim 7 , wherein the initial second counter value comprises zero.
9. A processor program for determining whether, for a datagram fragmented into at least two fragments, the at least two fragments are received, the processor program stored on a processor readable medium and comprising instructions to cause a processor to:
allocate memory to
a first counter value representing whether a final fragment is received, the first counter value based on more-fragments flags associated with the received at least two fragments, and
a second counter value representing receipt of a number of eight byte data units in the received at least two fragments,
based on the more-fragments flag associated with each received fragment,
determine that a received fragment is the final fragment and adjust the first counter value by one and adjust the second counter value by the fragment offset of the final fragment, or
determine that a received fragment is not the final fragment and adjust the second counter value by the number of eight byte data units comprised in the received fragment, and
based on the first counter value being different than an initial first counter value and the second counter value being equal to an initial second counter value, determine whether the at least two fragments are received.
10. The processor program of claim 9 , wherein the instructions to allocate comprise instructions to allocate fifteen bits of memory.
11. The processor program of claim 9 , wherein the instructions to adjust the first counter value comprise one of:
instructions to increment the first counter value by one, and
instructions to decrement the first counter value by one.
12. The processor program of claim 9 , wherein the instructions to adjust the second counter value by the fragment offset of the final fragment comprise one of:
instructions to increment the second counter value by the fragment offset, and
instructions to decrement the second counter value by the fragment offset.
13. The processor program of claim 9 , wherein the instructions to adjust the second counter value based on the number of eight byte data units comprised in the fragment comprise one of:
instructions to increment the second counter value by the number of eight byte data units comprised in the at least one fragment, and
instructions to decrement the second counter value by the number of eight byte data units comprised in the at least one fragment.
14. The processor program of claim 9 , wherein the initial second counter value comprises 2 13 .
15. The processor program of claim 9 , wherein the second counter comprises a sign.
16. The processor program of claim 15 , wherein the initial second counter value comprises zero.
17. A system for determining whether, for a datagram comprising at least two fragments, the at least two fragments are received, the system comprising
a first counter comprising a first counter value representing whether a final fragment is received, the first counter value based on more-fragments flags associated with the received at least two fragments,
a second counter comprising a second counter value representing receipt of a number of eight byte data units in the received at least two fragments, and
a digital data processing device in communication with the first counter and the second counter, the digital data processing device capable of:
based on the more-fragments flag associated with each received fragment,
determining that a received fragment is the final fragment and adjusting the first counter value by one and adjusting the second counter value by the fragment offset of the final fragment, or
determining that a received fragment is not the final fragment and adjusting the second counter value by the number of eight byte data units comprised in the received fragment, and
based on the first counter value being different than an initial first counter value and the second counter value being equal to an initial second counter value, determining whether the at least two fragments have been received.
18. The system of claim 17 , wherein the first counter comprises one bit of memory and the second counter comprises fourteen bits of memory.
19. The system of claim 17 , wherein the digital data processing device is capable of incrementing and decrementing the first and second counter values.
20. The system of claim 17 , wherein the initial second counter value comprises 2 13 .
21. The system of claim 17 , wherein the second counter comprises a sign.
22. The system of claim 21 , wherein the initial second counter value comprises zero.