Granted Patent B2

US 7,398,446 · App. 10/447,113 · Granted Jul 8, 2008

Abstract

Claims (29)

1. A method of generating interleaved addresses, comprising:

concurrently generating first and second interleaved addresses by a first interleaved address generator and a second interleaved address generator, respectively, wherein the generated second interleaved address is a next interleaved address with respect to the generated first interleaved address;

disabling the second interleaved address generator after the concurrently generating step;

enabling the second interleaved address generator to concurrently generate the second interleaved address with the first interleaved address generator generating the first interleaved address if the generated first interleaved address is an invalid interleaved address;

storing the generated first and second interleaved addresses;

first outputting the stored first interleaved address if the generated first interleaved address is invalid;

second outputting a next generated first interleaved address in a cycle subsequent to a cycle of the first outputting.

2. The method of claim 1 , further comprising:

third outputting the stored second interleaved address in a cycle subsequent to a cycle of the second outputting.

3. The method of claim 2 , further comprising:

fourth outputting the stored first interleaved address in cycles subsequent to a cycle of the third outputting if the stored first interleaved address is valid.

4. An apparatus for generating interleaved addresses, comprising:

a first interleaved address generator configured to generate a first interleaved address;

a second interleaved address generator configured to generate a second interleaved address substantially concurrently with the first interleaved address generator generating the first interleaved address; and

a controller configured to disable the second interleaved address generator from generating the second interleaved address after the first and second interleaved addresses have been generated.

5. The apparatus of claim 4 , wherein the first and second interleaved address generators are embodied as an interleaved address generator configured to selectively generate one or two interleaved address during a cycle of operation.

6. The apparatus of claim 4 , wherein the generated second interleaved address is a next interleaved address with respect to the generated first interleaved address.

7. The apparatus of claim 6 , wherein the controller enables the second interleaved address generator if the generated first interleaved address is an invalid interleaved address.

8. The apparatus of claim 7 , further comprising:

a first memory device storing the generated first interleaved address;

a second memory device storing the generated second interleaved address; and

a selector selectively outputting one of the generated first interleaved address, the stored first interleaved address and the stored second interleaved address.

9. The apparatus of claim 8 , wherein the controller controls the selector to first output the stored first interleaved address if the generated first interleaved address is invalid, and second output a next generated first interleaved address in a cycle subsequent to a cycle of the first outputting.

10. The apparatus of claim 9 , wherein the controller controls the selector to third output the stored second interleaved address in a cycle subsequent to a cycle of the second outputting.

11. The apparatus of claim 10 , wherein the controller controls the selector to fourth output the stored first interleaved address in cycles subsequent to a cycle of the third outputting if the stored first interleaved address is valid.

12. An apparatus for generating interleaved addresses, comprising:

a first interleaved address generator configured to generate a first interleaved address;

a second interleaved address generator configured to generate a second interleaved address substantially concurrently with the first interleaved address generator generating the first interleaved address; and

a controller configured to enable the second interleaved address generator for a single cycle if the first interleaved address is invalid.

Assignments (8)