Reduced surface field technique for semiconductor devices
View Patent ↗A power device and a method for manufacturing the same are provided. The power device comprises a first conductive semiconductor substrate; a second conductive buried layer formed to a certain depth within the semiconductor substrate; a second conductive epitaxial layer formed on the conductive buried layer; a first conductive well formed within the conductive epitaxial layer; a second conductive well formed within the second conductive epitaxial layer, on both sides of the first conductive well; a second conductive drift region formed in predetermined portions on the first and the second conductive well; and a lateral double diffused MOS transistor formed in the second conductive drift region. The breakdown voltage of the power device is controlled according to a distance between the first conductive well and the second conductive buried layer.
1. A power device comprising:
a semiconductor substrate;
a conductive buried layer formed within the semiconductor substrate;
a conductive epitaxial layer formed on the conductive buried layer;
a first conductive well formed within the conductive epitaxial layer;
a second conductive well formed within the conductive epitaxial layer, on at least two sides of the first conductive well;
a conductive drift region formed in predetermined portions on the first and the second conductive wells;
a lateral double diffused MOS transistor having a source region and a drain region formed in the conductive drift region; and
a conductive body region formed between the first conductive well and the source region;
wherein the conductive drift region lies between the second conductive well and the drain region.
2. The power device of claim 1 , wherein
the first conductive well and the conductive buried layer are embodied with a mutual distance predetermined responsive to a specified breakdown voltage criterion.
3. The power device of claim 1 , wherein the lateral double diffused MOS transistor comprises:
a gate insulating layer formed in a predetermined portion on the conductive drift region; and
a gate formed on the gate insulating layer;
wherein the conductive body region is formed in the conductive drift region to a side of the gate, the source region is formed within the conductive body region, and the drain region is formed in the conductive drift region.
4. The power device of claim 3 , wherein the gate insulating layer comprises a thick oxide layer and a thin oxide layer connected to a side of the thick oxide layer.
5. The power device of claim 3 , wherein the source region further comprises a conductive high-concentration source contact region.
6. The power device of claim 3 , further comprising a conductive junction region located in the source region having a high doping concentration.
7. The power device of claim 1 , further comprising an isolation region formed outside the second conductive well.
8. The power device of claim 7 , wherein the isolation region comprises an isolation conductive region comprising high-concentration dopant formed at a surface of the semiconductor substrate through the conductive buried layer.
9. The power device of claim 1 , wherein the first conductive well is P type and the second conductive well is N type.