IP Library Granted Patent US 7,587,656
Granted Patent B2
US 7,587,656 · App. 10/447,923 · Granted Sep 8, 2009

Method and apparatus for detecting and correcting errors in stored information

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Quick Facts
Patent No.
US 7,587,656
App. No.
10/447,923
Granted
Sep 8, 2009
Kind
B2
Abstract

A device can receive information to be stored in a first part of a first portion of a block, read previously-stored information from a second part, and store the specified information in the first part and simulate storage of the previously-stored information in the second part while generating error detection information which is then stored in a second portion of the block. The device can read a specified subset of sections in a block, use part of each section to detect and/or correct an error in another part thereof, while avoiding reading the error detection information unless a section in the subset has an uncorrected error. Detected errors are corrected with successive correction stages, while maintaining for each section being processed in the stages a count of the number of other sections which are thereafter read in succession without error.

Claims (59)

1. An apparatus, comprising:

a storage portion which a plurality of blocks, each block including a data portion and a residue portion,

wherein the residue portion is used to store block-level error correction information corresponding to information stored in the data portion;

a circuit portion which includes instructions stored therein to:

write information to and read information from said storage portion, and

perform a simulated write to said storage portion wherein no information is actually written; said circuit portion including:

a block-level error correction generator portion configured to generate block-level error correction information when said circuit portion writes information to said storage portion, and generate block-level error correction information when said circuit portion performs a simulated write to said storage portion; and

a sector-level error correction generator portion configured to generate sector-level error correction information when said circuit portion writes information to said storage portion;

wherein said circuit portion includes instructions stored therein to:

receive user data to be stored in a first part of the data portion of a specified block;

read previously-stored user data from a second part of the data portion of the specified block and buffering the user data from the second part of the data portion the specified block, wherein the second part includes all of the data portion of the specified block other than the first part thereof;

write the received user data to the first part of the data portion of the specified block, causing said sector-level error correction generator portion to generate sector-level error correction information corresponding to the received user data, and causing said block-level error correction generator portion to generate block-level error correction information corresponding to the received user data;

write the sector-level error correction information to the first part of the data portion of the specified block;

perform a simulated write of the previously-stored user data to the second part of the data portion of the specified block, causing said block-level error correction generator portion to generate block-level error correction information corresponding to the previously-stored user data; and

write the block-level error correction information corresponding to the received user data and the previously-stored user data to the residue portion of the specified block.

2. An apparatus according to claim 1 , wherein said circuit portion includes instructions stored therein to:

write the received user data in its entirety to the first part of the data portion of the specified block, and

perform a simulated write of the previously-stored user data in its entirety to the second part of the data portion of the specified block.

3. An apparatus according to claim 1 , wherein:

the previously-stored user data of the second part of the data portion of the specified block includes first and second segments; and

said circuit portion includes instructions stored therein to:

perform a simulated write of the first segment in its entirety to the second part of the data portion of the specified block,

write the received user data in its entirety to the first part of the data portion of the specified block, and

perform a simulated write of the second segment in its entirety to the second part of the data portion of the specified block.

4. An apparatus according to claim 1 , wherein

said circuit portion includes instructions stored therein to:

perform a simulated write of the previously-stored user data in its entirety to the second part, and

write the received user data in its entirety to the first part.

5. An apparatus according to claim 1 , wherein:

said storage portion includes a rotatable disk with a plurality of tracks; and

the plurality of tracks includes a plurality of concentric tracks.

6. An apparatus according to claim 1 , wherein said circuit portion includes instructions stored therein to:

pause said block-level error correction generator portion on the occurrence of an exception while said block-level error correction generator portion is generating the block-level error correction information,

restart a write of the received user data to the first part of the data portion of the specified block and perform a simulated write of the previously-stored user data to the second part of the specified block, and

enable said block-level error correction generator portion at the point in the process which corresponds to the occurrence of the exception.

7. The apparatus of claim 1 , wherein:

the data portion of each block includes a plurality of sectors; and

the residue portion of each block includes another plurality of sectors.

8. A method of operating an apparatus having a storage portion which includes a plurality of blocks, each block including a data portion, and a residue portion used to store information facilitating corrections of errors in information stored in the data portion, the method comprising:

receiving user data to be written to a first part of the data portion of a specified block;

reading previously-stored user data from a second part of the data portion of the specified block and buffering the user data from the second part of the data portion of the specified block, wherein the second part includes all of the data of the specified block other than said first part thereof;

writing the received user data to the first part, causing a generation of block-level and sector-level error correction information corresponding to the received user data;

writing the sector-level error correction information to the first part;

simulating a writing of the previously-stored user data to the second part, causing a generation of block-level error correction information corresponding to the previously-stored user data without actually writing the previously-stored user data to the second part; and

writing the block-level error correction information corresponding to the received user data and the previously-stored user data to the residue portion of the specified block.

9. A method according to claim 8 , wherein said writing of received user data and said simulating a writing of the previously-stored user data is carried out by writing the received user data in its entirety to the first part, and simulating the writing of the previously-stored user data in its entirety to the second part.

10. A method according to claim 8 , wherein:

the previously-stored user data from the second part of the data portion includes first and second segments; and

said writing of the received user data and said simulating a writing of the previously-stored user data is carried out by:

simulating a writing of the first segment in its entirety to the second part of the data portion of the specified block, writing the received user data in its entirety to the first part of the data portion of the specified block, and

simulating a writing of the second segment in its entirety to the second part of the data portion of the specified block.

11. A method according to claim 8 , wherein said writing of the received user data and said simulating a writing of the previously-stored user data is carried out by simulating a writing of the previously-stored user data in its entirety to the first part of the data portion of the specified block, and writing the received user data in its entirety to the second part of the data portion of the specified block.

12. A method according to claim 8 , including:

responding to an occurrence of an exception during said generating of said error correction information by:

pausing the generation of the block-level error correction information,

restarting said writing of the received user data to the first part and said simulating a writing of the previously-stored user data to the second part, and

enabling the generation of the block-level error correction information at the point in the process which corresponds to the occurrence of said exception.

13. A method according to claim 8 , including carrying out said simulating a writing of the previously-stored user data in less time than would be needed for actually writing the previously-stored user data to the second part.

14. The method of claim 8 , wherein no further reading is performed after said reading.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL USA L.P.; ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2016
From: EMC CORPORATION
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 040203/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2010
From: IOMEGA CORPORATION
To: EMC CORPORATION
Reel/Frame 023953/0328 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2003
From: LARSEN, TROY D.; CULLEY, MARTIN L.; DEFOREST, MARVIN R.
To: IOMEGA CORPORATION
Reel/Frame 014127/0717 →