Wide-bandwidth, high-dynamic-range linear amplifier for a CDMA transmitter in a wireless base station
View Patent ↗A CDMA base station transmitter employing the Kahn envelope-elimination-and-restoration technique includes a switching amplifier adapted to linearly amplify the low-level baseband signal derived from the digital amplitude information portion of the digital CDMA signal to be transmitted downlink. In order to achieve the wide bandwidth and high dynamic range needed to linearly amplify the low-level baseband signal derived from the digital amplitude portion of the CDMA signal, a truncating circuit truncates a predetermined number of the least significant bits of each word of the digital amplitude portion before the amplitude portion is converted to a low-level baseband signal and is amplified by the switching amplifier. High resolution is restored to the amplified output by a power-dissipating post regulator at the output of the switching amplifier.
1. A transmitter that produces a power-amplified phase- and amplitude-modulated output in response to an input signal, the transmitter comprising:
a switching amplifier that linearly amplifies an applied amplitude portion of the input signal; and
a power amplifier that amplitude modulates an amplified phase portion of the input signal in accordance with a least one applied modulating signal derived at least in part from the linearly amplified applied amplitude portion of the input signal produced by the switching amplifier;
wherein the transmitter further comprises:
means for reducing the resolution of the amplitude portion of the input signal applied to the switching amplifier, the output of the switching amplifier having the reduced resolution of the applied amplitude portion; and
means responsive to the reduced-resolution output of the switching amplifier and to the full-resolution amplitude portion of the input signal for restoring the full resolution of the amplitude portion of the input signal back into the modulating signal applied to the power amplifier.
2. The transmitter of claim 1 wherein the input signal is a digital signal comprising a predetermined number of bits per word, and the means for reducing the resolution comprises means for truncating a predetermined number of least significant bits in each word of the input signal.
3. The transmitter of claim 1 wherein the responsive means comprises a post regulator to which the output of the switching amplifier and a signal derived from the full-resolution amplitude portion of the input signal are applied, the post regulator dissipating power in the output of the switching amplifier to drive its resolution to the full-resolution of the amplitude portion of the input signal.
4. The transmitter of claim 1 where the responsive means comprises means for applying the reduced-resolution output of the switching amplifier to a high-level modulation input of the power amplifier, and for applying a signal derived from the full-resolution input signal to a control element of the power amplifier.
5. The transmitter of claim 4 wherein the power amplifier comprises a circuit containing an FET and the output of the switching amplifier is applied to a drain of the FET and the signal derived from the full-resolution input signal is applied to a gate of the FET.
6. The transmitter of claim 4 wherein the power amplifier comprises a circuit containing a bi-polar transistor and the output of the switching amplifier is applied to a collector of the transistor and the signal derived from the full-resolution input signal is applied to a base of the transistor.
7. The transmitter of claim 4 wherein the power amplifier comprises a circuit containing a vacuum tube and the output of the switching amplifier is applied to a plate of the vacuum tube and the full-resolution input signal is applied to a grid of the vacuum tube.
8. The transmitter of claim 2 wherein transmitter is in a base station of a wireless communication system and the input signal is a CDMA signal.
9. The transmitter of claim 1 wherein the switching amplifier is a class D amplifier.
10. The transmitter of claim 1 wherein the switching amplifier is a class S amplifier.
11. An amplifier circuit for linearly amplifying a high-resolution input signal, the amplifier circuit comprising:
means for reducing the full resolution of the input signal;
a switching amplifier for linearly amplifying the reduced-resolution input signal; and
means responsive to a reduced-resolution output of the switching amplifier and to the full resolution input signal for restoring the full resolution of the input signal back into the amplified output signal of the switching amplifier
wherein the means for restoring the full resolution comprises a post regulator to which the output of the switching amplifier and a signal derived from the full-resolution input signal are applied, the post regulator dissipating power in the output of the switching amplifier to drive its resolution to the full-resolution of the input signal.
12. The amplifier circuit of claim 11 wherein the input signal is a digital signal comprising a predetermined number of bits, and the means for reducing the resolution comprises means for truncating a predetermined number of least significant bits in each word of the input signal.
13. The amplifier circuit of claim 11 wherein the switching amplifier is a class D amplifier.
14. The amplifier circuit of claim 11 wherein the switching amplifier is a class S amplifier.